M74HC4020 14 STAGE BINARY COUNTER HIGH SPEED : f = 70 MHz (TYP.) at V = 6V MAX CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t PLH PHL ORDER CODES WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC4020B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC4020M1R M74HC4020RM13TR 74 SERIES 4020 TSSOP M74HC4020TTR DESCRIPTION The M74HC4020 is an high speed CMOS 14 For M74HC4020 twelve kind of divided output are STAGE BINARY COUNTER fabricated with provided 1st and 4th stage to 14th stage. 2 silicon gate C MOS technology. The maximum division available at last stage is A clear input is used to reset the counter to the all 1/16384 x f at clock. IN low level state. A high level on CLEAR All inputs are equipped with protection circuits accomplishes the reset function. A negative against static discharge and transient excess transition on the CLOCK input increments the voltage. counter by one. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11M74HC4020 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 9, 7, 6, 5, 3, Q1, Q4 to 2, 4, 13, 12, Parallel Outputs Q14 14, 15, 1 Clock Input (LOW to 10 CLOCK HIGH, Edge Triggered) 11 CLEAR Reset Inputs 8 GND Ground (0V) 16 Vcc Positive Supply Voltage TRUTH TABLE CLOCK CLEAR OUTPUT STATE X H ALL OUTPUTS = L NO CHANGE L ADVANCE TO NEXT STATE LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11