ST7570TR

ST7570 S-FSK power line networking system-on-chip Datasheet production data Features Fully integrated narrow-band power line networking system-on-chip High performing PHY processor with embedded turn-key firmware for spread frequency shift keying (S-FSK) modulation: 6&1&0. X X , Programmable bit rate up to 2.4 Kbps ( PITCH 50 Hz) 1 Hz step programmable carriers up to Suitable for EN50065 and FCC part 15 148.5 kHz compliant applications Signal to noise ratio estimation VFQFPN48 package with exposed pad Received signal strength indication -40 C to +85 C temperature range Protocol engine embedding: IEC61334-5-1 PHY and MAC layers Applications Alarm management Smart metering applications Repeater Call procedure Intelligent search initiator process Street lighting control On chip peripherals: Command and control networking Host controller UART interface Fully integrated analog front end: Description ADC and DAC The ST7570 is a powerful power line networking PGA with automatic gain control for high system-on-chip. It combines a high-performance receiving sensitivity PHY processor core and a protocol controller core High linearity modulated signal generation with a fully integrated analog front end (AFE) and line driver. Fully integrated single-ended power amplifier for line driving The ST7570 features allow the most cost- Up to 1 A rms, 14 V p-p output effective, single-chip power line communication Configurable Active filtering topology solution based on IEC61334-5-1 S-FSK standard. Very high linearity Embedded temperature sensor Table 1. Device summary Current control feature Order codes Package Packaging 8 to 18 V power amplifier supply ST7570 Tube VFQFPN48 3.3 V or 5 V digital I/O supply ST7570TR Tape and reel Integrated 5 V and 1.8 V linear regulators for AFE and digital core supply Mains zero crossing synchronization September 2012 Doc ID 17526 Rev 2 1/26 This is information on a product in full production. www.st.com 26Contents ST7570 Contents 1 Device overview 3 2 Pin connection 4 2.1 Pin description 5 3 Maximum ratings 8 3.1 Absolute maximum ratings . 8 3.2 Thermal data . 8 4 Electrical characteristics . 9 5 Analog front end (AFE) 13 5.1 Reception path . 13 5.2 Transmission path 13 5.3 Power amplifier . 14 5.4 Current and voltage control . 15 5.5 Thermal shutdown and temperature control . 16 5.6 Zero-crossing PLL and delay compensation 16 6 Power management . 17 7 Clock management . 18 8 Functional overview 18 8.1 References 19 9 Physical layer . 20 9.1 S-FSK principles . 20 9.2 Bit timing 21 9.3 Frame structure at physical level . 22 9.4 Frame timing and time-slot synchronization . 22 10 Package mechanical data 23 11 Revision history . 25 2/26 Doc ID 17526 Rev 2