STW81200T STMicroelectronics

STW81200 Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs Datasheet - production data Low power functional mode Supply voltage: 3.0 V to 5.4 V Small size exposed pad VFQFPN36 package 6 x 6 x 1.0 mm VFQFPN36 Process: BICMOS 0.25 m SiGe Applications Features Cellular/4G infrastructure equipment Output frequency range: 46.875 to 6000 MHz Instrumentation and test equipment Very low noise Cable TV Normalized in band phase noise floor: -227 dBc/Hz Other wireless communication systems VCO phase noise: -135 dBc/Hz 1 MHz Table 1. Device summary offset, 4.0 GHz carrier Order Code Package Packing Noise floor: -160 dBc/Hz Dual architecture frequency synthesizer: STW81200T VFQFPN36 Tray Fractional-N and Integer-N STW81200TR VFQFPN36 Tape and reel Integrated VCOs with automatic center frequency calibration Description Programmable RF output dividers by The STW81200 is a dual architecture frequency 1/2/4/8/16/32/64 synthesizer (Fractional-N and Integer-N), that Dual RF Output broadband matched with features three low phase-noise VCOs with a programmable power level and mute function fundamental frequency range of 3.0 GHz to External VCO option with 5 V charge pump 6.0 GHz and a programmable dual RF output divider stage which allows coverage from Integrated low noise LDO voltage regulators 46.875 MHz to 6 GHz. Maximum phase detector frequency: 100 MHz The STW81200 optimizes size and cost of the Exact frequency mode final application thanks to the integration of low- Fast lock and cycle slip reduction noise LDO voltage regulators and internally- Differential reference clock input (LVDS and matched broadband RF outputs. LVECPL compliant) supporting up to 800 MHz The STW81200 is compatible with a wide range 13-bit programmable reference frequency of supply voltages (from 3.0 V to 5.4 V) providing divider to the end user a very high level of flexibility which trades off excellent performance with power Programmable charge pump current dissipation requirements. A low-power functional Digital lock detector mode (software controlled) gives an extra power Integrated reference crystal oscillator core saving. R/W SPI interface Additional features include crystal oscillator core, Logic compatibility/tolerance 1.8 V/3.3 V external VCO mode and output-mute function. August 2019 DS10185 Rev 8 1/61 www.st.comContents STW81200 Contents 1 Functional block diagram . 6 2 Pin definitions 7 3 Absolute maximum ratings 10 4 Operating conditions . 11 5 Electrical specifications . 13 6 Typical performance characteristics . 19 7 Circuit description 24 7.1 Reference input stage . 24 7.2 Reference divider . 24 7.3 PLL N divider 25 7.3.1 Fractional spurs and compensation mechanism 26 7.4 Phase frequency detector (PFD) . 27 7.5 Lock detect 28 7.6 Charge pump 28 7.7 Fast lock mode . 29 7.8 Cycle slip reduction . 29 7.9 Voltage controlled oscillators (VCOs) 29 7.10 RF output divider stage 30 7.11 Low-power functional modes 31 7.12 LDO voltage regulators 32 7.13 STW81200 register programming 33 7.14 STW81200 register summary 35 7.15 STW81200 register descriptions . 36 7.16 Power ON sequence 51 7.17 Example of register programming 51 2/61 DS10185 Rev 8