Data Sheet Rev.1.2 14.08.2012 4096MB DDR3 SDRAM ECC SO-DIMM 204 Pin ECC SO-UDIMM Features: 204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double SGN04G72G1BD2SA-xx(W)RT Data Rate synchronous DRAM Module 4GByte in FBGA Technology Module organization: dual rank 512M x 72 V = 1.5V 0.075V, V 1.5V 0.075V DD DDQ RoHS compliant 1.5V I/O ( SSTL 15 compatible) Fly-by-bus with termination for C/A & CLK bus On-board I2C temperature sensor with integrated serial Options: presence-detect (SPD) EEPROM Gold-contact pad Data Rate / Latency Marking This module is fully pin and functional compatible to the DDR3 1066 MT/s CL7 -BB JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM DDR3 1333 MT/s CL9 -CC design spec. and JEDEC- Standard MO-268. (see DDR3 1600 MT/s CL11 -DC www.jedec.org) The pcb and all components are manufactured according Module density to the RoHS compliance specification 4096MB with 18 dies and 2 rank EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS) Standard Grade (T ) 0C to 70C A (T ) 0C to 85C C DDR3 - SDRAM component Samsung K4B2G0846D Grade W (T ) -40C to 85C A 256Mx8 DDR3 SDRAM in PG-TFBGA-78 package (T ) -40C to 95C C 8-bit prefetch architecture Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type. *) The refresh rate has to be doubled when 85C<T <95C C On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity. Environmental Requirements: Refresh, Self Refresh and Power Down Modes. Operating temperature (ambient) ZQ Calibration for output driver and ODT. Standard Grade 0C to 70C System Level Timing Calibration Support via Write W-Grade -40C to 85C Leveling and Multi Purpose Register (MPR) Read Pattern. Operating Humidity 10% to 90% relative humidity, noncondensing 1 Figure: mechanical dimensions Operating Pressure 105 to 69 kPa (up to 10000 ft.) Storage Temperature -55C to 100C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50C 1 if no tolerances specified 0.15mm Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 1 CH 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info swissbit.com of 17 Data Sheet Rev.1.2 14.08.2012 This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line Memory Module (SO-UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK ). READ and WRITE accesses to a DDR3 SDRAM module is burst-oriented accesses start at a selected location and Figure 1: Mechanical Dimensions continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving power- down mode. All inputs and all full drive-strength outputs are SSTL 15 compatible. The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM 2 using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the modules organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Row Device Bank Column Module Organization DDR3 SDRAMs used Refresh Addr. Addr. Addr. Bank Select 512M x 72bit 18 x 256M x 8bit (2048Mbit) 15 BA0, BA1, BA2 10 8k S0 , S1 Module Dimensions in mm 67.60 (long) x 30(high) x 3.80 max (thickness) Timing Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SGN04G72G1BD2SA-BB W RT 4096MB 8.5 GB/s 1.87ns/1066MT/s 7-7-7 SGN04G72G1BD2SA-CC W RT 4096MB 10.6 GB/s 1.5ns/1333MT/s 9-9-9 SGN04G72G1BD2SA-DC W RT 4096MB 12.8 GB/s 1.25ns/1600MT/s 11-11-11 Pin Name A0 A9, A11 A14 Address Inputs A10/AP Address Input / Autoprecharge Bit BA0 BA2 Bank Address Inputs DQ0 DQ63 Data Input / Output CB0 CB07 ECC check bits DM0 DM8 Input Data Mask DQS0 DQS8 Data Strobe, positive line DQS0 - DQS8 Data Strobe, negative line (only used when differential data strobe mode is enabled) RAS Row Address Strobe CAS Column Address Strobe WE Write Enable CKE0 CKE1 Clock Enable S0 , S1 Chip Select CK0 CK1 Clock Inputs, positive line CK0 - CK1 Clock Inputs, negative line Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 2 CH 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info swissbit.com of 17