74HC138D Toshiba

74HC138D CMOS Digital Integrated Circuits Silicon Monolithic 74HC138D74HC138D74HC138D74HC138D 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description 3-to-8 Line Decoder 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 - Y7) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) High speed: t = 16 ns (typ.) at V = 5 V pd CC (2) Low power dissipation: I = 4.0 A (max) at T = 25 CC a (3) Balanced propagation delays: t t PLH PHL (4) Wide operating voltage range: V = 2.0 to 6.0 V CC(opr) 4. 4. 4. 4. PackagingPackagingPackagingPackaging SOIC16 Start of commercial production 2016-03 2016 Toshiba Corporation 2016-08-04 1 Rev.3.074HC138D 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 7. IEC Logic Symbol 7. 7. 7. IEC Logic SymbolIEC Logic SymbolIEC Logic Symbol 2016 Toshiba Corporation 2016-08-04 2 Rev.3.0