Product Information

74VHC573FT

74VHC573FT electronic component of Toshiba

Datasheet
Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP

Manufacturer: Toshiba
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

2500: USD 0.1804 ea
Line Total: USD 451

0 - Global Stock
MOQ: 2500  Multiples: 2500
Pack Size: 2500
Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 24 May to Thu. 30 May

MOQ : 2500
Multiples : 2500

Stock Image

74VHC573FT
Toshiba

2500 : USD 0.6846
5000 : USD 0.6789
10000 : USD 0.6735
15000 : USD 0.6678
20000 : USD 0.6622
25000 : USD 0.6566
30000 : USD 0.6509
50000 : USD 0.6452
100000 : USD 0.6395

0 - WHS 2


Ships to you between Fri. 24 May to Thu. 30 May

MOQ : 2500
Multiples : 2500

Stock Image

74VHC573FT
Toshiba

2500 : USD 0.2332

     
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74VHC573FT CMOS Digital Integrated Circuits Silicon Monolithic 74VHC573FT74VHC573FT74VHC573FT74VHC573FT 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description Octal D-Type Latch with 3-State Outputs 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74VHC573FT is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). When the OE input is high, the eight outputs are in a high impedance state. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: T = -40 to 125 opr (3) High speed: t = 4.5 ns (typ.) at V = 5.0 V pd CC (4) Low power dissipation: I = 4.0 A (max) at T = 25 CC a (5) High noise immunity: V = V = 28% V (min) NIH NIL CC (6) Power-down protection is provided on all inputs. (7) Balanced propagation delays: t t PLH PHL (8) Wide operating voltage range: V = 2.0 V to 5.5 V CC(opr) (9) Low noise: V = 1.0 V (max) OLP (10) Pin and function compatible with the 74 series (74AC/HC/AHC/LV etc.) 573 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 4. 4. 4. 4. PackagingPackagingPackagingPackaging TSSOP20B Start of commercial production 2013-03 2016 Toshiba Corporation 2017-02-22 1 Rev.4.074VHC573FT 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 7. 7. 7. 7. IEC Logic SymbolIEC Logic SymbolIEC Logic SymbolIEC Logic Symbol 2016 Toshiba Corporation 2017-02-22 2 Rev.4.0

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