TC74HC74AF(F) Toshiba

TC74HC74AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC74AP,TC74HC74AF,TC74HC74AFN Dual D-Type Flip Flop Preset and Clear Note: xxxFN (JEDEC SOP) is not available in Japan. The TC74HC74A is a high speed CMOS D FLIP FLOP 2 TC74HC74AP fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CLOCK pulse. CLEAR and PRESET are independent of the CLOCK and are accomplished by setting the appropriate input to an L level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74HC74AF Features High speed: f = 77 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 2 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL TC74HC74AFN Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2~6 V CC Pin and function compatible with 74LS74 Pin Assignment Weight DIP14-P-300-2.54 : 0.96 g (typ.) SOP14-P-300-1.27A : 0.18 g (typ.) SOL14-P-150-1.27 : 0.12 g (typ.) 1 2007-10-01 TC74HC74AP/AF/AFN IEC Logic Symbol Truth Table Inputs Outputs Function CLR PR D CK Q Q L H X X L H Clear H L X X H L Preset L L X X H H H H L L H H H H H L H H X Q Q No Change n n X: Dont care System Diagram 2 2007-10-01