TC74LVX138FT(SPL) Toshiba

TC74LVX138F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LVX138F, TC74LVX138FT 3-to-8 Line Decoder TC74LVX138F The TC74LVX138F/ FT is a high-speed CMOS 3-to-8 line decoder fabricated with silicon gate CMOS technology. Designed for use in 3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. This device is suitable for low-voltage and battery operated systems. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade TC74LVX138FT connection and for use as an address decoder for memory systems. An input protection circuit ensures that 0 to 5.5V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features Weight High-speed: t = 5.5 ns (typ.) (V = 3.3 V) pd CC SOP16-P-300-1.27A : 0.18 g (typ.) Low power dissipation: I = 4 A (max) (Ta = 25C) TSSOP16-P-0044-0.65A : 0.06 g (typ.) CC Input voltage level: V = 0.8 V (max) (V = 3 V) IL CC V = 2.0 V (min) (V = 3 V) IH CC Power-down protection provided on all inputs Balanced propagation delays: t t pLH pHL Pin and function compatible with 74HC138 Start of commercial production 1993-01 1 2014-03-01 TC74LVX138F/FT Pin Assignment (top view) A 1 16 V CC B 2 15 Y0 C 14 Y1 3 G2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 IEC Logic Symbol Bin/Oct Dmux (1) (15) (1) (15) A 1 0 Y0 A 0 0 Y0 (2) (14) (2) (14) 0 B 2 1 Y 1 B 1 Y 1 G (3) (13) (3) (13) 7 C 4 2 Y 2 C 2 2 Y 2 (12) (12) 3 Y3 3 Y3 (11) (11) & & 4 Y 4 4 Y 4 (6) (10) (6) (10) G1 5 Y5 G1 5 Y5 (4) (9) (4) (9) G2A EN 6 Y6 G2A EN 6 Y6 (5) (7) (5) (7) G2B 7 Y 7 G2B 7 Y 7 Truth Table Inputs Outputs Enable Select Selected Output Y 0 Y1 Y2 Y3 Y4 Y5 Y6 Y 7 G1 G2A G2B C B A L X X X X X H H H H H H H H None X H X X X X H H H H H H H H None X X H X X X H H H H H H H H None H L L L L L L H H H H H H H Y 0 H L L L L H H L H H H H H H Y 1 H L L L H L H H L H H H H H Y 2 H L L L H H H H H L H H H H Y 3 H L L H L L H H H H L H H H Y 4 H L L H L H H H H H H L H H Y 5 H L L H H L H H H H H H L H Y 6 H L L H H H H H H H H H H L Y 7 X: Dont care 2 2014-03-01