W65C816S6TQG-14

November 09, 2018 W65C816S 8/16 bit Microprocessor WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it must be the responsibility of the user to determine the suitability of the products for each application. WDC products are not authorized for use as critical components in life support devices or systems. Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright (C) 1981-2018 by The Western Design Center, Inc. All rights reserved, including the right of reproduction in whole or in part in any form. November 09, 2018 TABLE OF CONTENTS 1 INTRODUCTION ...................................................................................................... 5 1.1 Features of the W65C816S ......................................................................................................... 5 2 W65C816S FUNCTIONAL DESCRIPTION ............................................................. 6 2.1 Instruction Register (IR) ............................................................................................................. 6 2.2 Timing Control Unit (TCU) .......................................................................................................... 6 2.3 Arithmetic and Logic Unit (ALU)................................................................................................ 6 2.4 Accumulator (A) .......................................................................................................................... 6 2.5 Data Bank Register (DBR) .......................................................................................................... 6 2.6 Direct (D) ...................................................................................................................................... 7 2.7 Index (X and Y) ............................................................................................................................ 7 2.8 Processor Status Register (P) ................................................................................................... 7 2.9 Program Bank Register (PBR) ................................................................................................... 7 2.10 Program Counter (PC) ................................................................................................................ 7 2.11 Stack Pointer (S) ......................................................................................................................... 7 2.12 Pin Function Description .......................................................................................................... 10 2.13 Abort (ABORTB) ........................................................................................................................ 12 2.14 Address Bus (A0-A15) .............................................................................................................. 12 2.15 Bus Enable (BE) ........................................................................................................................ 12 2.16 Data/Bank Address Bus (D0-D7) ............................................................................................. 13 2.17 Emulation Status (E) ................................................................................................................. 13 2.18 Interrupt Request (IRQB) .......................................................................................................... 13 2.19 Memory Lock (MLB) .................................................................................................................. 13 2.20 Memory/Index Select Status (MX) ........................................................................................... 13 2.21 Non-Maskable Interrupt (NMIB) ............................................................................................... 14 2.22 Phase 2 In (PHI2) ....................................................................................................................... 14 2.23 Read/Write (RWB) ..................................................................................................................... 14 2.24 Ready (RDY)............................................................................................................................... 14 2.25 Reset (RESB) ............................................................................................................................. 15 2.26 Valid Data Address (VDA) and Valid Program Address (VPA) ............................................. 15 2.27 VDD and VSS ............................................................................................................................. 15 2.28 Vector Pull (VPB) ....................................................................................................................... 15 3 ADDRESSING MODES ......................................................................................... 16 3.1 Reset and Interrupt Vectors ..................................................................................................... 16 3.2 Stack ........................................................................................................................................... 16 3.3 Direct .......................................................................................................................................... 16 3.4 Program Address Space .......................................................................................................... 16 3.5 Data Address Space ................................................................................................................. 16 3.5.1 Absolute-a ................................................................................................................................. 17 3.5.2 Absolute Indexed Indirect-(a,x) ................................................................................................. 17 3.5.3 Absolute Indexed with X-a,x ...................................................................................................... 17 3.5.4 Absolute Indexed with Y-a,y ...................................................................................................... 17 3.5.5 Absolute Indirect-(a) .................................................................................................................. 18 3.5.6 Absolute Long Indexed With X-al,x ........................................................................................... 18 3.5.7 Absolute Long-al ........................................................................................................................ 18 3.5.8 Accumulator-A ........................................................................................................................... 18 3.5.9 Block Move-xyc ......................................................................................................................... 19 3.5.10 Direct Indexed Indirect-(d,x) .................................................................................................... 19 3.5.11 Direct Indexed with X-d,x ........................................................................................................ 20 3.5.12 Direct Indexed with Y-d,y ........................................................................................................ 20 2