Product Information

W29N08GVBIAA

W29N08GVBIAA electronic component of Winbond

Datasheet
NAND Flash 4G-bit NAND flash, 3V x 8bit
Manufacturer: Winbond
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1

MOQ : 210
Multiples : 210

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W29N08GVBIAA
Winbond

210 : USD 20.1718
420 : USD 19.9868
840 : USD 19.803
1050 : USD 19.6179
2100 : USD 19.4329
2520 : USD 19.2478
5040 : USD 19.0627
10500 : USD 18.8764
105000 : USD 18.69
N/A

Obsolete
0 - WHS 2

MOQ : 1
Multiples : 1

Stock Image

W29N08GVBIAA
Winbond

1 : USD 13.0487
10 : USD 11.6025
25 : USD 11.3416
50 : USD 11.2763
N/A

Obsolete

Read More Specifications

     
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RoHS - XON
Icon ROHS
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Memory Size
Interface Type
Organisation
Data Bus Width
Supply Voltage - Min
Supply Voltage - Max
Supply Current - Max
Minimum Operating Temperature
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Additional Infomation About Product

W29N08GV 2 CHIP STACKED 8G-BIT W29N08GV 8G-BIT 3.3V NAND FLASH MEMORY th Release Date: May 17 , 2018 1 Revision C W29N08GV Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................ 7 2. FEATURES .................................................................................................................................... 7 3. PACKAGE TYPES AND PIN CONFIGURATIONS ....................................................................... 8 3.1 Pin Assignment W29N08GVSIAA 1CE Type 48-pin TSOP1 ............................................... 8 3.2 Pin Assignment W29N08GVSIAD 2CE Type 48-pin TSOP1 ............................................... 9 3.3 Pin Assignment W29N08GVBIAA 1CE Type 63-ball VFBGA ............................................ 10 3.4 Pin Assignment W29N08GVBIAD 2CE Type 63-ball VFBGA ............................................ 11 3.5 Pin Descriptions .................................................................................................................. 12 4. PIN DESCRITPIONS ................................................................................................................... 13 4.1 Chip Enable ( CE) .............................................................................................................. 13 4.2 Write Enable ( WE) ............................................................................................................ 13 4.3 Read Enable ( RE) ............................................................................................................. 13 4.4 Address Latch Enable (ALE) .............................................................................................. 13 4.5 Command Latch Enable (CLE) ........................................................................................... 13 4.6 Write Protect ( WP) ............................................................................................................ 13 4.7 Ready/Busy (RY/ BY) ........................................................................................................ 13 4.8 Input and Output (I/Ox) ....................................................................................................... 13 5. SINGLE DIE BLOCK DIAGRAM .................................................................................................. 14 6. MEMORY ARRAY ORGANIZATION ........................................................................................... 15 6.1 Array Organization ............................................................................................................ 15 7. MODE SELECTION TABLE ........................................................................................................ 16 8. COMMAND TABLE ...................................................................................................................... 17 9. DEVICE OPERATIONS ............................................................................................................... 19 9.1 READ operation .................................................................................................................. 19 9.1.1 PAGE READ (00h-30h) ........................................................................................................ 19 9.1.2 CACHE READ OPERATIONS .............................................................................................. 19 9.1.3 TWO PLANE READ (00h-00h-30h) ...................................................................................... 23 9.1.4 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 25 9.1.5 READ ID (90h) ...................................................................................................................... 27 9.1.6 READ PARAMETER PAGE (ECh) ....................................................................................... 28 9.1.7 READ STATUS (70h) ........................................................................................................... 30 9.1.8 READ STATUS ENHANCED (78h) ...................................................................................... 32 9.1.9 READ UNIQUE ID (EDh) ...................................................................................................... 33 9.2 PROGRAM operation ......................................................................................................... 34 9.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 34 9.2.2 SERIAL DATA INPUT (80h) ................................................................................................. 34 9.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 35 9.2.4 CACHE PROGRAM (80h-15h) ............................................................................................. 35 9.2.5 TWO PLANE PAGE PROGRAM .......................................................................................... 37 9.3 COPY BACK operation ....................................................................................................... 40 9.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 40 9.3.2 PROGRAM for COPY BACK (85h-10h) ................................................................................ 40 9.3.3 TWO PLANE READ for COPY BACK ................................................................................... 41 th Release Date: May 17 , 2018 2 Revision C

HS Compliance

Tariff Desc

8542.32.00 32 No ..CMOS and MOS Read Only Memory and Programmable Read Only Memory whether erasable or non-erasable (for example, flash memory, EPROM, E2PROM, EAPROM, NOVRAM, ROM and PROM)

Winbond may also be referenced as

Winbond Elec
WINBOND ELECTRONICS
WINBOND ELECTRONICS CORP AMERICA

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