EK-U1-ZCU102-G

ZCU102 Evaluation Board User Guide UG1182 (v1.6) June 12, 2019Revision History The following table shows the revision history for this document. Date Version Revision 06/12/2019 1.6 Chapter 3, Board Component Descriptions. Replaced Table 3-7. Updated HDMI Video Output in Chapter 3. Updated Figure 3-23. Updated Table 3-30 for pin B1. Added HDMI Video Input section. Enhanced Figure A-1. 01/11/2019 1.5 Changed DDR4 72-bit to DDR4 64-bit in Figure 1-1 and PS-Side: DDR4 SODIMM Socket in Chapter 3. Removed ECC from Board Features. Updated Table 2-1, callout 2, with DDR4 SODIMM and updated the Micron part number (MTA4ATF51264HZ-2G6E1). Updated Markings. 10/04/2018 1.4 Updated Figure 2-1 and Figure 2-2. Added Electrostatic Discharge Caution in Chapter 2. Updated schematic number in Table 2-1. Updated SFP0-SFP3 functions in Table 2-3. Updated callout in Cooling Fan Connector in Chapter 3. Updated descriptions in PS-Side: DDR4 SODIMM Socket and PL-Side: DDR4 Component Memory in Chapter 3. Updated Ports 0 and 4 I2C address in Table 3-23. Added Note in SFP/SFP+ Connector in Chapter 3. Updated Bank info in SFP+ in Chapter 3. Updated I/O Standard for AE5 and AF5 in Table 3-52. Updated Appendix B, Xilinx Design Constraints. Updated Appendix C, Regulatory and Compliance Information. Updated XTP433 and XTP435 links and added DS925 and ZCU102 Design Hub link in Appendix D, Additional Resources and Legal Notices. 08/02/2017 1.3 Updated logic cell and CLB flip-flop resource count in Table 1-1. Added Note 2 to Table 2-2. Changed maximum PL internal supply voltage from 0.875V to 0.876V in Table 3-1. Updated GTR REF CLK USB3 frequency in Table 3-12. Added I2C addresses to Table 3-23 and Table 3-24. Clarified third paragraph under HDMI Clock Recovery in Chapter 3. 03/20/2017 1.2 Added notes to Dimensions in Chapter 1. Updated SW6 default switch setting in Table 2-2 and SD configuration setting in Table 2-4. Clarified SW6 4:1 boot mode pin settings under Quad-SPI and SD in Chapter 2. Changed DDR SODIMM Memory J1 heading to DDR Component Memory in Table 3-4. Changed PS REF CLK frequency from 33 MHz to 33.33 MHz in Table 3-12. Changed UART2 RTS O B to UART2 CTS O B in Table 3-16. Replaced Figure 3-16. Changed QSPI119 (LWR), U120 (UPR) heading to MSP430 U41 in Figure 3-17. Clarified references to Figure 3-17 in Table 3-19 and Table 3-20. Added addresses to titles in Table 3-21 and Table 3-22 and headings in Table 3-23 and Table 3-24. Changed 22 to L22 in Table 3-28. Updated GTH connectivity for Quad 128, Quad 228, Quad 229, and Quad 23 under GTH Transceivers in Chapter 3. Updated bank assignments in Figure 3-36. Added callout 44 to Switches in Chapter 3. Updated Xilinx websites in Appendix D, Additional Resources and Legal Notices. ZCU102 Evaluation Board User Guide 2 Send Feedback UG1182 (v1.6) June 12, 2019 www.xilinx.com