25 R XC18V00 Series In-System-Programmable Configuration PROMs 0 DS026 (v6.1) February 5, 2019 Product Specification Features In-System Programmable 3.3V PROMs for Low-Power Advanced CMOS FLASH Process Configuration of Xilinx FPGAs Dual Configuration Modes Endurance of 20,000 Program/Erase Cycles Serial Slow/Fast Configuration (up to 33 MHz) Program/Erase Over Full Industrial Voltage and Parallel (up to 264 Mb/s at 33 MHz) Temperature Range (40C to +85C) 5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals IEEE Std 1149.1 Boundary-Scan (JTAG) Support 3.3V or 2.5V Output Capability JTAG Command Initiation of Standard FPGA Design Support Using the Xilinx ISE Foundation Configuration Software Packages Simple Interface to the FPGA Available in PC20, SO20, PC44, and VQ44 Packages Cascadable for Storing Longer or Multiple Bitstreams Lead-Free (Pb-Free) Packaging Description Xilinx introduces the XC18V00 series of in-system When the FPGA is in Master SelectMAP mode, the FPGA programmable configuration PROMs (Figure 1). Devices in generates a configuration clock that drives the PROM. When this 3.3V family include a 4-megabit, a 2-megabit, a the FPGA is in Slave Parallel or Slave SelectMAP mode, an 1-megabit, and a 512-kilobit PROM that provide an easy-to- external oscillator generates the configuration clock that use, cost-effective method for reprogramming and storing drives the PROM and the FPGA. After CE and OE are Xilinx FPGA configuration bitstreams. enabled, data is available on the PROMs DATA (D0-D7) pins. New data is available a short access time after each When the FPGA is in Master Serial mode, it generates a rising clock edge. The data is clocked into the FPGA on the configuration clock that drives the PROM. A short access following rising edge of the CCLK. A free-running oscillator time after CE and OE are enabled, data is available on the can be used in the Slave Parallel or Slave SelecMAP modes. PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each Multiple devices can be cascaded by using the CEO output rising clock edge. The FPGA generates the appropriate to drive the CE input of the following device. The clock number of clock pulses to complete the configuration. When inputs and the DATA outputs of all PROMs in this chain are the FPGA is in Slave Serial mode, the PROM and the FPGA interconnected. All devices are compatible and can be are clocked by an external clock. cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family. X-Ref Target - Figure 1 CLK CE OE/RESET TCK CEO Data Control Serial TMS and Data D0 DATA or Memory Serial or Parallel Mode JTAG TDI Address Parallel Interface 7 Interface D 1:7 TDO Parallel Interface CF DS026 01 040204 Figure 1: XC18V00 Series Block Diagram 19992019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. DS026 (v6.1) February 5, 2019 www.xilinx.com Send Feedback Product Specification 1R XC18V00 Series In-System-Programmable Configuration PROMs Pinout and Pin Description Table 1 provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC packages. Table 1: Pin Names and Descriptions 20-pin Pin Boundary- 44-pin Function Pin Description 44-pin VQFP SOIC & Name Scan Order PLCC PLCC D0 4 DATA OUT D0 is the DATA output pin to provide data for 40 2 1 configuring an FPGA in serial mode. 3OUTPUT ENABLE D1 6 DATA OUT D0-D7 are the output pins to provide parallel 29 35 16 data for configuring a Xilinx FPGA in Slave 5OUTPUT Parallel/SelectMAP mode. ENABLE D1-D7 remain in high-Z state when the PROM D2 2 DATA OUT 42 4 2 operates in serial mode. D1-D7 can be left unconnected when the 1OUTPUT PROM is used in serial mode. ENABLE D3 8 DATA OUT 27 33 15 7OUTPUT ENABLE (1) D4 24 DATA OUT 9 15 7 23 OUTPUT ENABLE D5 10 DATA OUT 25 31 14 9OUTPUT ENABLE D6 17 DATA OUT 14 20 9 16 OUTPUT ENABLE D7 14 DATA OUT 19 25 12 13 OUTPUT ENABLE CLK 0 DATA IN Each rising edge on the CLK input increments 43 5 3 the internal address counter if both CE is Low and OE/RESET is High. OE/ 20 DATA IN When Low, this input holds the address 13 19 8 RESET counter reset and the DATA output is in a high- 19 DATA OUT Z state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. 18 OUTPUT Polarity is NOT programmable. ENABLE CE 15 DATA IN When CE is High, the device is put into low- 15 21 10 power standby mode, the address counter is reset, and the DATA pins are put in a high-Z state. (1) CF 22 DATA OUT Allows JTAG CONFIG instruction to initiate 10 16 7 FPGA configuration without powering down 21 OUTPUT FPGA. This is an open-drain output that is ENABLE pulsed Low by the JTAG CONFIG command. DS026 (v6.1) February 5, 2019 www.xilinx.com Send Feedback Product Specification 2