1 Spartan-3A DSP FPGA Family Data Sheet DS610 October 4, 2010 Product Specification Module 1: Introduction and Ordering Information DS610 (v3.0) October 4, 2010 Introduction UG431: XtremeDSP DSP48A for Spartan-3A DSP Features FPGAs User Guide Architectural Overview DSP48A Slice Design Considerations Configuration Overview DSP48A Architecture Highlights General I/O Capabilities - 18 x 18-Bit Multipliers Supported Packages and Package Marking - 48-Bit Accumulator Ordering Information - 18-bit Pre-Adder DSP48A Application Examples Module 2: Functional Description Module 3: DS610 (v3.0) October 4, 2010 DC and Switching Characteristics DS610 (v3.0) October 4, 2010 The functionality of the Spartan-3A DSP FPGA family is described in the following documents. DC Electrical Characteristics UG331: Spartan-3 Generation FPGA User Guide Absolute Maximum Ratings Clocking Resources Supply Voltage Specifications Digital Clock Managers (DCMs) Recommended Operating Conditions Block RAM Switching Characteristics Configurable Logic Blocks (CLBs) I/O Timing - Distributed RAM Configurable Logic Block (CLB) Timing - SRL16 Shift Registers Digital Clock Manager (DCM) Timing - Carry and Arithmetic Logic Block RAM Timing I/O Resources XtremeDSP Slice Timing Programmable Interconnect ISE Software Design Tools and IP Cores Configuration and JTAG Timing Embedded Processing and Control Solutions Module 4: Pin Types and Package Overview Pinout Descriptions Package Drawings Powering FPGAs DS610 (v3.0) October 4, 2010 Power Management Pin Descriptions UG332: Spartan-3 Generation Configuration User Guide Package Overview Configuration Overview Pinout Tables Configuration Pins and Behavior Footprint Diagrams Bitstream Sizes Detailed Descriptions by Mode - Master Serial Mode using Platform Flash PROM - Master SPI Mode using Commodity Serial Flash - Master BPI Mode using Commodity Parallel Flash - Slave Parallel (SelectMAP) using a Processor - Slave Serial using a Processor - JTAG Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device DNA Copyright 20072010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS610 October 4, 2010 www.xilinx.com Product Specification 16 Spartan-3A DSP FPGA Family: Introduction and Ordering Information DS610 (v3.0) October 4, 2010 Product Specification Introduction Hierarchical SelectRAM memory architecture The Spartan-3A DSP family of Field-Programmable Gate Arrays Up to 2268 Kbits of fast block RAM with byte write enables (FPGAs) solves the design challenges in most high- volume, for processor applications cost-sensitive, high-performance DSP applications. The Up to 373 Kbits of efficient distributed RAM two-member family offers densities ranging from 1.8 to 3.4 million Registered outputs on the block RAM with operation of at system gates, as shown in Table 1. least 280 MHz in the standard -4 speed grade Dual-range V supply simplifies 3.3V-only design The Spartan-3A DSP family builds on the success of the CCAUX Suspend, Hibernate modes reduce system power Spartan-3A FPGA family by increasing the amount of memory per Low-power option reduces quiescent current logic and adding XtremeDSP DSP48A slices. New features Multi-voltage, multi-standard SelectIO interface pins improve system performance and reduce the cost of configuration. Up to 519 I/O pins or 227 differential signal pairs These Spartan-3A DSP FPGA enhancements, combined with LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O proven 90 nm process technology, deliver more functionality and 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling bandwidth per dollar than ever before, setting the new standard in Selectable output drive, up to 24 mA per pin the programmable logic and DSP processing industry. QUIETIO standard reduces I/O switching noise Full 3.3V 10% compatibility and hot swap compliance The Spartan-3A DSP FPGAs extend and enhance the Spartan-3A 622+ Mb/s data transfer rate per differential I/O FPGA family. The XC3SD1800A and the XC3SD3400A devices LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with are tailored for DSP applications and have additional block RAM integrated differential termination resistors and XtremeDSP DSP48A slices. The XtremeDSP DSP48A slices Enhanced Double Data Rate (DDR) support replace the 18x18 multipliers found in the Spartan-3A devices and DDR/DDR2 SDRAM support up to 333 Mb/s are based on the DSP48 blocks found in the Virtex-4 devices. Fully compliant 32-/64-bit, 33/66 MHz PCI support Abundant, flexible logic resources The block RAMs are also enhanced to run faster by adding an Densities up to 53712 logic cells, including optional shift output register. Both the block RAM and DSP48A slices in the register Spartan-3A DSP devices run at 250 MHz in the lowest cost, Efficient wide multiplexers, wide logic, fast carry logic standard -4 speed grade. IEEE 1149.1/1532 JTAG programming/debug port Because of their exceptional DSP price/performance ratio, Eight Digital Clock Managers (DCMs) Spartan-3A DSP FPGAs are ideally suited to a wide range of Clock skew elimination (delay locked loop) consumer electronics applications, such as broadband access, Frequency synthesis, multiplication, division High-resolution phase shifting home networking, display/projection, and digital television. Wide frequency range (5 MHz to over 320 MHz) The Spartan-3A DSP family is a superior alternative to mask Eight low-skew global clock networks, eight additional clocks programmed ASICs. FPGAs avoid the high initial cost, lengthy per half device, plus abundant low-skew routing development cycles, and the inherent inflexibility of conventional Configuration interface to industry-standard PROMs ASICs. Also, FPGA programmability permits design upgrades in Low-cost, space-saving SPI serial Flash PROM the field with no hardware replacement necessary, an impossibility x8 or x8/x16 BPI parallel NOR Flash PROM with ASICs. Low-cost Xilinx Platform Flash with JTAG Unique Device DNA identifier for design authentication Load multiple bitstreams under FPGA control Features Post-configuration CRC checking Very low cost, high-performance DSP solution for MicroBlaze and PicoBlaze embedded processor cores high-volume, cost-conscious applications BGA and CSP packaging with Pb-free options 250 MHz XtremeDSP DSP48A Slices Common footprints support easy density migration Dedicated 18-bit by 18-bit multiplier XA Automotive version available Available pipeline stages for enhanced performance of at least 250 MHz in the standard -4 speed grade 48-bit accumulator for multiply-accumulate (MAC) operation Integrated adder for complex multiply or multiply-add operation Integrated 18-bit pre-adder Optional cascaded Multiply or MAC Table 1: Summary of Spartan-3A DSP FPGA Attributes CLB Array (One CLB = Four Slices) Distributed Block Maximum System Equivalent Total Total RAM RAM Maximum Differential (1) (1) Device Gates Logic Cells Rows Columns CLBs Slices Bits Bits DSP48As DCMs User I/O I/O Pairs XC3SD1800A 1800K 37,440 88 48 4,160 16,640 260K 1512K 84 8 519 227 XC3SD3400A 3400K 53,712 104 58 5,968 23,872 373K 2268K 126 8 469 213 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. Copyright 20072010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 2