0 R Virtex-5 Family Overview 00 DS100 (v5.1) August 21, 2015 Product Specification General Description Using the second generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO technology with built-in digitally-controlled impedance, ChipSync source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability. Summary of Virtex-5 FPGA Features Five platforms LX, LXT, SXT, TXT, and FXT Advanced DSP48E slices Virtex-5 LX: High-performance general logic applications 25 x 18, twos complement, multiplication Optional adder, subtracter, and accumulator Virtex-5 LXT: High-performance logic with advanced serial Optional pipelining connectivity Virtex-5 SXT: High-performance signal processing Optional bitwise logical functionality applications with advanced serial connectivity Dedicated cascade connections Virtex-5 TXT: High-performance systems with double Flexible configuration options density advanced serial connectivity SPI and Parallel FLASH interface Virtex-5 FXT: High-performance embedded systems with Multi-bitstream support with dedicated fallback advanced serial connectivity reconfiguration logic Cross-platform compatibility Auto bus width detection capability LXT, SXT, and FXT devices are footprint compatible in the System Monitoring capability on all devices same package using adjustable voltage regulators On-chip/Off-chip thermal monitoring Most advanced, high-performance, optimal-utilization, On-chip/Off-chip power supply monitoring FPGA fabric JTAG access to all monitored quantities Real 6-input look-up table (LUT) technology Integrated Endpoint blocks for PCI Express Designs Dual 5-LUT option LXT, SXT, TXT, and FXT Platforms Improved reduced-hop routing Compliant with the PCI Express Base Specification 1.1 64-bit distributed RAM option x1, x4, or x8 lane support per block SRL32/Dual SRL16 option Works in conjunction with RocketIO transceivers Powerful clock management tile (CMT) clocking Tri-mode 10/100/1000 Mb/s Ethernet MACs Digital Clock Manager (DCM) blocks for zero delay LXT, SXT, TXT, and FXT Platforms buffering, frequency synthesis, and clock phase shifting RocketIO transceivers can be used as PHY or connect to PLL blocks for input jitter filtering, zero delay buffering, external PHY using many soft MII (Media Independent Interface) options frequency synthesis, and phase-matched clock division RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s 36-Kbit block RAM/FIFOs LXT and SXT Platforms True dual-port RAM blocks RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s Enhanced optional programmable FIFO logic TXT and FXT Platforms Programmable PowerPC 440 Microprocessors - True dual-port widths up to x36 - Simple dual-port widths up to x72 FXT Platform only RISC architecture Built-in optional error-correction circuitry 7-stage pipeline Optionally program each block as two independent 18-Kbit 32-Kbyte instruction and data caches included blocks Optimized processor interface structure (crossbar) High-performance parallel SelectIO technology 65-nm copper CMOS process technology 1.2 to 3.3V I/O Operation 1.0V core voltage Source-synchronous interfacing using ChipSync High signal-integrity flip-chip packaging available in standard technology or Pb-free package options Digitally-controlled impedance (DCI) active termination Flexible fine-grained I/O banking High-speed memory interface support 20062015 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, UltraScale, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. PowerPC is a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners. DS100 (v5.1) August 21, 2015 www.xilinx.com Product Specification 1R Virtex-5 Family Overview Table 1: Virtex-5 FPGA Family Members Configurable Logic Blocks (CLBs) Block RAM Blocks Max RocketIO Endpoint (6) PowerPC Transceivers Total Max DSP48E Blocks for Ethernet (4) Device Max CMTs Processor I/O User (2) (5) Array Virtex-5 Slices Max PCI MACs (3) (8) (7) Distributed 18 Kb 36 Kb Blocks Banks I/O (1) (Row x Col) Slices (Kb) Express GTP GTX RAM (Kb) XC5VLX30 80 x 30 4,800 320 32 64 32 1,152 2 N/A N/A N/A N/A N/A 13 400 XC5VLX50 120 x 30 7,200 480 48 96 48 1,728 6 N/A N/A N/A N/A N/A 17 560 XC5VLX85 120 x 54 12,960 840 48 192 96 3,456 6 N/A N/A N/A N/A N/A 17 560 XC5VLX110 160 x 54 17,280 1,120 64 256 128 4,608 6 N/A N/A N/A N/A N/A 23 800 XC5VLX155 160 x 76 24,320 1,640 128 384 192 6,912 6 N/A N/A N/A N/A N/A 23 800 XC5VLX220 160 x 108 34,560 2,280 128 384 192 6,912 6 N/A N/A N/A N/A N/A 23 800 XC5VLX330 240 x 108 51,840 3,420 192 576 288 10,368 6 N/A N/A N/A N/A N/A 33 1,200 XC5VLX20T 60 x 26 3,120 210 24 52 26 936 1 N/A 1 2 4 N/A 7 172 XC5VLX30T 80 x 30 4,800 320 32 72 36 1,296 2 N/A 1 4 8 N/A 12 360 XC5VLX50T 120 x 30 7,200 480 48 120 60 2,160 6 N/A 1 4 12 N/A 15 480 XC5VLX85T 120 x 54 12,960 840 48 216 108 3,888 6 N/A 1 4 12 N/A 15 480 XC5VLX110T 160 x 54 17,280 1,120 64 296 148 5,328 6 N/A 1 4 16 N/A 20 680 XC5VLX155T 160 x 76 24,320 1,640 128 424 212 7,632 6 N/A 1 4 16 N/A 20 680 XC5VLX220T 160 x 108 34,560 2,280 128 424 212 7,632 6 N/A 1 4 16 N/A 20 680 XC5VLX330T 240 x 108 51,840 3,420 192 648 324 11,664 6 N/A 1 4 24 N/A 27 960 XC5VSX35T 80 x 34 5,440 520 192 168 84 3,024 2 N/A 1 4 8 N/A 12 360 XC5VSX50T 120 x 34 8,160 780 288 264 132 4,752 6 N/A 1 4 12 N/A 15 480 XC5VSX95T 160 x 46 14,720 1,520 640 488 244 8,784 6 N/A 1 4 16 N/A 19 640 XC5VSX240T 240 x 78 37,440 4,200 1,056 1,032 516 18,576 6 N/A 1 4 24 N/A 27 960 XC5VTX150T 200 x 58 23,200 1,500 80 456 228 8,208 6 N/A 1 4 N/A 40 20 680 XC5VTX240T 240 x 78 37,440 2,400 96 648 324 11,664 6 N/A 1 4 N/A 48 20 680 XC5VFX30T 80 x 38 5,120 380 64 136 68 2,448 2 1 1 4 N/A 8 12 360 XC5VFX70T 160 x 38 11,200 820 128 296 148 5,328 6 1 3 4 N/A 16 19 640 XC5VFX100T 160 x 56 16,000 1,240 256 456 228 8,208 6 2 3 4 N/A 16 20 680 XC5VFX130T 200 x 56 20,480 1,580 320 596 298 10,728 6 2 3 6 N/A 20 24 840 XC5VFX200T 240 x 68 30,720 2,280 384 912 456 16,416 6 2 4 8 N/A 24 27 960 Notes: 1. Virtex-5 FPGA slices are organized differently from previous generations. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops (previously it was two LUTs and two flip-flops.) 2. Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator. 3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18-Kbit blocks. 4. Each Clock Management Tile (CMT) contains two DCMs and one PLL. 5. This table lists separate Ethernet MACs per device. 6. RocketIO GTP transceivers are designed to run from 100 Mb/s to 3.75 Gb/s. RocketIO GTX transceivers are designed to run from 150Mb/s to 6.5 Gb/s. 7. This number does not include RocketIO transceivers. 8. Includes configuration Bank 0. 2 www.xilinx.com DS100 (v5.1) August 21, 2015 Product Specification