XC9572-15PCG84C

PRODUCT OBSOLETE / UNDER OBSOLESCENCE 0 R XC9572 In-System Programmable CPLD 05 DS065 (v5.0) May 17, 2013 Product Specification Features Description 7.5 ns pin-to-pin logic delays on all pins The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for f to 125 MHz CNT general purpose logic integration. It is comprised of eight 72 macrocells with 1,600 usable gates 36V18 Function Blocks, providing 1,600 usable gates with Up to 72 user I/O pins propagation delays of 7.5 ns. See Figure 2 for the architec- 5V in-system programmable ture overview. - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and Power Management temperature range Power dissipation can be reduced in the XC9572 by config- Enhanced pin-locking architecture uring macrocells to standard or low-power modes of opera- Flexible 36V18 Function Block tion. Unused macrocells are turned off to minimize power - 90 product terms drive any or all of 18 macrocells dissipation. within Function Block Operating current for each design can be approximated for - Global and product term clocks, output enables, specific operating conditions using the following equation: set and reset signals I (mA) = MC (1.7) + MC (0.9) + MC (0.006 mA/MHz) f CC HP LP Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Where: Programmable power reduction mode in each MC = Macrocells in high-performance mode HP macrocell MC = Macrocells in low-power mode Slew rate control on individual outputs LP User programmable ground pin capability MC = Total number of macrocells used Extended pattern security features for design f = Clock frequency (MHz) protection Figure 1 shows a typical calculation for the XC9572 device. High-drive 24 mA outputs 3.3V or 5V I/O capability 200 Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one (160) XC9500 concurrently Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages (125) 100 (100) (65) 050 100 Clock Frequency (MHz) DS065 01 110501 Figure 1: Typical I vs. Frequency for XC9572 CC 1998, 20032006, 2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at PRODUCT OBSOLETE / UNDER OBSOLESCENCE R XC9572 In-System Programmable CPLD 3 JTAG In-System Programming Controller 1 JTAG Port Controller 36 Function 18 Block 1 I/O Macrocells I/O 1 to 18 I/O 36 I/O Function 18 Block 2 Macrocells 1 to 18 I/O Blocks I/O 36 Function I/O 18 Block 3 Macrocells I/O 1 to 18 I/O 3 I/O/GCK 36 Function 1 18 Block 4 I/O/GSR 2 Macrocells I/O/GTS 1 to 18 DS065 02 110101 Figure 2: XC9572 Architecture Function block outputs (indicated by the bold line) drive the I/O blocks directly. 2 www.xilinx.com DS065 (v5.0) May 17, 2013 Product Specification Fast CONNECT II Switch Matrix