XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JUNE 2006 REV. 1.0.1 the receiver this is accomplished with internal GENERAL DESCRIPTION resistors or through the combination of one single The XRT83SL30 is a fully integrated single-channel fixed value external resistor and programmable short-haul line interface unit for T1(1.544Mbps) 100, internal resistors. In the absence of the power supply, E1(2.048Mbps) 75 or 120 and J1 110 the transmit output and receive input are tri-stated applications. allowing for redundancy applications. The chip includes an integrated programmable clock multiplier In T1 applications, the XRT83SL30 can generate five that can synthesize T1 or E1 master clocks from a transmit pulse shapes to meet the short-haul Digital variety of external clock sources. Cross-Connect (DSX-1) template requirements. APPLICATIONS The XRT83SL30 provides both Serial Host microprocessor interface and Hardware Mode for T1 Digital Cross-Connects (DSX-1) programming and control. Both B8ZS and HDB3 ISDN Primary Rate Interface encoding and decoding functions are included and can be disabled as required. On-chip crystal-less jitter CSU/DSU E1/T1/J1 Interface attenuator with a 32 or 64 bit FIFO can be placed T1/E1/J1 LAN/WAN Routers either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83SL30 Public switching Systems and PBX Interfaces provides a variety of loop-back and diagnostic T1/E1/J1 Multiplexer and Channel Banks features as well as transmit driver short circuit detection and receive loss of signal monitoring. It FEATURES supports internal impedance matching for 75, 100, (See Page 2) 110 and 120 for both transmitter and receiver. For FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL30 T1/E1/J1 LIU (HOST MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 TAOS DRIVE DMO ENABLE MONITOR QRSS TTIP TPOS / TDATA HDB3/ TX FILTER PATTERN TX/RX JITTER TIMING LINE B8ZS & PULSE TNEG / CODES GENERATOR ATTENUATOR CONTROL DRIVER ENCODER SHAPER TRING TCLK LBO 3:0 TXON LOCAL QRSS ENABLE ANALOG REMOTE DIGITAL LOOPBACK LOOPBACK LOOPBACK LOOPBACK QRSS QRPD ENABLE DETECTOR RCLK HDB3/ TIMING & PEAK TX/RX JITTER RX RTIP RNEG / LCV B8ZS DATA DETECTOR ATTENUATOR EQUALIZER RRING DECODER RECOVERY & SLICER RPOS / RDATA NETWORK LOS AIS NLCD LOOP NLCD ENABLE EQUALIZER DETECTOR DETECTOR DETECTOR CONTROL RLOS AISD TEST ICT HW/HOST SDO CS Serial Interface SCLK INT SDI RESET Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com JA SELECTXRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 FIGURE 2. BLOCK DIAGRAM OF THE XRT83SL30 T1/E1/J1 LIU (HARDWARE MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 CLKSEL 2:0 TAOS DRIVE TXTEST 0:2 DFM DMO ENABLE MONITOR INSBPV QRSS TPOS / TDATA TTIP HDB3/ TX FILTER PATTERN TX/RX JITTER TIMING LINE B8ZS & PULSE TNEG / CODES GENERATOR ATTENUATOR CONTROL DRIVER ENCODER SHAPER TCLK TRING LBO 3:0 LOCAL TXON QRSS ENABLE ANALOG REMOTE DIGITAL LOOPBACK LOOPBACK LOOPBACK LOOPBACK QRSS QRPD ENABLE DETECTOR RCLK HDB3/ TIMING & PEAK RTIP TX/RX JITTER RX B8ZS DATA DETECTOR RNEG / LCV ATTENUATOR EQUALIZER RRING DECODER RECOVERY & SLICER RPOS / RDATA LOOP1 NETWORK EQUALIZER LOS AIS LOOP0 LOOP NLCD ENABLE NLCD DETECTOR DETECTOR CONTROL DETECTOR AISD RLOS TEST ICT HW/HOST JABW GAUGE TRATIO JASEL1 SR/DR JASEL0 RXTSEL EQC 4:0 HARWARE CONTROL TCLKE TXTSEL TERSEL1 RCLKE RXMUTE TERSEL0 ATAOS RXRES1 RESET RXRES0 FEATURES Fully integrated single-channel short-haul transceiver for E1,T1 or J1 applications Programmable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform generator for transmit output pulse shaping High receiver interference immunity Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for both T1 and E1 modes Supports 75 and 120 (E1), 100 (T1) and 110 (J1) applications. Internal and/or external impedance matching for 75,100, 110 and 120. Tri-State transmit output and receive input capability for redundancy applications Provides High Impedance for Tx and Rx during power off Transmit return loss meets or exceeds ETSI 300 166 standard On-chip digital clock recovery circuit for high input jitter tolerance Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO Selectable either in transmit or receive path On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO) Receive loss of signal (RLOS) output On-chip HDB3/B8ZS/AMI encoder/decoder QRSS pattern generation and detection for testing and monitoring Error and Bipolar Violation Insertion and Detection 2 JA SELECT