16GB (x72, ECC, DR) 288-Pin DDR4 VLP UDIMM Features DDR4 SDRAM VLP UDIMM MTA18ADF2G72AZ 16GB Figure 1: 288-Pin VLP UDIMM (MO-309) Features Module height: 18.75mm (0.738in) DDR4 functionality and operations supported as defined in the component data sheet 288-pin, very low profile unbuffered dual in-line memory module (VLP UDIMM) Options Marking Fast data transfer rates: PCB4-3200, PC4-2666, or PC4-2400 Operating temperature Commercial None 16GB (2 Gig x 72) (0C T 95C) OPER V = 1.20V (NOM) DD Package V = 2.5V (NOM) PP 288-pin DIMM (halogen-free) Z V = 2.5V (NOM) DDSPD Frequency/CAS latency Supports ECC error detection and correction 0.62ns CL = 22 (DDR4-3200) -3G2 Nominal and dynamic on-die termination (ODT) for 0.75ns CL = 19 (DDR4-2666) -2G6 data, strobe, and mask signals 0.83ns CL = 17 (DDR4-2400) -2G3 Low-power auto self refresh (LPASR) Data bus inversion (DBI) for data bus On-die V generation and calibration REFDQ Dual-rank 2 On-board I C temperature sensor with integrated serial presence-detect (SPD) EEPROM 4 internal device bank groups with 4 banks per group produce 16 device banks Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Gold edge contacts Halogen-free Fly-by topology Terminated control, command, and address bus Table 1: Key Timing Parameters Data Rate (MT/s) CL = t t t 10 RCD RP RC PC4- 24 22 21 20 19 18 17 16 15 14 13 12 11 9 (ns) (ns) (ns) -3G2 3200 3200, 3200, 2666 2666 2400 2400 2133 2133 1866 1866 1600 1600 1333 13.75 13.75 45.75 2933 2933 -2G9 2933 2933 2933 2666 2666 2400 2400 2133 2133 1866 1866 1600 1600 1333 14.32 14.32 46.32 CCMTD-1725822587-10359 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 adf18c2gx72az.pdf Rev. E 5/18 EN 2016 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Speed Grade16GB (x72, ECC, DR) 288-Pin DDR4 VLP UDIMM Features Table 1: Key Timing Parameters (Continued) Data Rate (MT/s) CL = t t t 10 RCD RP RC PC4- 24 22 21 20 19 18 17 16 15 14 13 12 11 9 (ns) (ns) (ns) -2G6 2666 2666 2666 2400 2400 2133 2133 1866 1866 1600 1600 1333 14.16 14.16 46.16 -2G3 2400 2400 2400 2133 2133 1866 1866 1600 1600 1333 14.16 14.16 46.16 -2G1 2133 2133 2133 1866 1866 1600 1600 1333 13.5 13.5 46.5 1333 Table 2: Addressing Parameter 16GB Row address 64K A 15:0 Column address 1K A 9:0 Device bank group address 4 BG 1:0 Device bank address per group 4 BA 1:0 Device configuration 8Gb (1 Gig x 8), 16 banks Module rank address 2 CS n 1:0 Table 3: Part Numbers and Timing Parameters 16GB Modules 1 Base device: MT40A1G8, 8Gb DDR4 SDRAM Module Module Memory Clock/ Clock Cycles 2 t t Part Number Density Configuration Bandwidth Data Rate (CL- RCD- RP) MTA18ADF2G72AZ-3G2 16GB 2 Gig x 72 25.6 GB/s 0.62ns/3200MT/s 22-22-22 MTA18ADF2G72AZ-2G6 16GB 2 Gig x 72 21.3 GB/s 0.75ns/2666MT/s 19/19/19 MTA18ADF2G72AZ-2G3 16GB 2 Gig x 72 19.2 GB/s 0.83ns/2400 MT/s 17-17-17 Notes: 1. The data sheet for the base device can be found at micron.com. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MTA18ADF2G72AZ-3G2E1. CCMTD-1725822587-10359 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 adf18c2gx72az.pdf Rev. E 5/18 EN 2016 Micron Technology, Inc. All rights reserved. Speed Grade