March 2004 AS7C31024B 3.3V 128K X 8 CMOS SRAM Features Industrial and commercial temperatures Easy memory expansion with CE1, CE2, OE inputs Organization: 131,072 words x 8 bits TTL/LVTTL-compatible, three-state I/O High speed 32-pin JEDEC standard packages - 300 mil SOJ - 10/12/15/20 ns address access time - 400 mil SOJ - 5, 6, 7, 8 ns output enable access time - 8 20mm TSOP 1 Low power consumption: ACTIVE - 8 x 13.4mm sTSOP 1 - 252 mW / max 10 ns ESD protection 2000 volts Low power consumption: STANDBY Latch-up current 200 mA - 18 mW / max CMOS 6T 0.18u CMOS technology Pin arrangement 32-pin SOJ (300 mil) Logic block diagram 32-pin SOJ (400 mil) V NC 1 32 CC A15 A16 2 31 CE2 A14 3 30 A12 4 29 WE V A7 5 28 CC A13 A6 6 27 A8 GND A5 7 26 A9 A11 A4 8 25 Input buffer A3 9 24 OE A10 A2 10 23 A1 11 22 CE1 A0 12 21 I/O7 A0 I/O0 13 20 I/O6 A1 I/O7 I/O1 14 19 I/O5 A2 I/O2 15 18 I/O4 512 x 256 x 8 A3 GND 16 17 I/O3 A4 Array A5 32-pin (8 x 20mm) TSOP I (1,048,576) A6 32-pin (8 x 13.4mm) sTSOP1 A7 I/O0 A8 A11 1 32 OE A9 2 31 A10 A8 3 30 CE1 A13 4 29 I/O7 WE Column decoder 5 28 WE I/O6 Control OE 6 27 CE2 I/O5 7 A15 26 I/O4 CE1 circuit 8 25 I/O3 V CC CE2 9 24 GND NC 10 A16 23 I/O2 11 22 A14 I/O1 12 21 A12 I/O0 13 20 A7 A0 14 19 A6 A1 18 15 A5 A2 17 16 A4 A3 Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns Maximum operating current 70656055 mA Maximum CMOS standby current 5 5 5 5 mA 3/24/04, v.1.2 Alliance Semiconductor P. 1 of 9 Copyright 2003 Alliance Semiconductor. All rights reserved. Row decoder A9 A10 A11 A12 A13 A14 A15 A16 Sense amp AS7C31024B AS7C31024BAS7C31024B Functional description The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5, 6, 7, 8 ns are ideal for AA RC WC OE high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume I power. If the bus is SB static, then full standby power is reached (I ). For example, the AS7C31024B is guaranteed not to exceed 18 mW under nominal full SB1 standby conditions. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V -0.50 +5.0 V CC t1 Voltage on any pin relative to GND V 0.50 V +0.50 V t2 CC Power dissipation P 1.0 W D Storage temperature (plastic) T 65 +150 C stg Ambient temperature with V applied T 55 +125 C CC bias DC current into outputs (low) I 20 mA OUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 CE2 WE OE Data Mode HXXX High Z Standby (I , I ) SB SB1 X L X X High Z Standby (I , I ) SB SB1 L H H H High Z Output disable (I ) CC LH HL D Read (I ) OUT CC LHLX D Write ( ) IN ICC Key: X = dont care, L = low, H = high 3/24/04, v.1.2 Alliance Semiconductor P. 2 of 9