September 2006 AS7C31025C
Advance Information
3.3V 128K X 8 CMOS SRAM (Center power and ground)
Features
Industrial and commercial temperatures
- 32-pin, 300 mil SOJ
Organization: 131,072 x 8 bits
- 32-pin, 400 mil SOJ
High speed
- 32-pin, TSOP 2
- 10 ns address access time
ESD protection 2000 volts
- 5 ns output enable access time
Low power consumption via ship deselect
Easy memory expansion with CE, OE inputs
Center power and ground
TTL/LVTTL-compatible, three-state I/O
JEDEC-standard packages
Pin arrangement
32-pin TSOP 2
A0 1 32 A16
A1 2 31
Logic block diagram A15
A2 3 30
A14
A3 4 29
A13
CE 28
5
OE
6 27
V I/O0
I/O7
CC
26
I/O1 7
I/O6
V 8 25
GND CC GND
24
GND 9
V
CC
I/O2 10 23
Input buffer I/O5
I/O3 11 22
I/O4
WE 12 21
A12
A4 13 20
A0 A11
14 19
A5 A10
A1 I/O7
18
A6 15 A9
A2
131,072 x 8
17
A7 16 A8
A3
Array
A4
A5 (1,048,576)
32-pin SOJ (300 mil)
A6
32-pin SOJ (400 mil)
A7
I/O0
A16
A8
A0 1
32
31 A15
A1 2
A2 3 30 A14
WE A3 4
29 A13
Control
CE 5
28 OE
Address decoder
OE
I/O0 6
27 I/O7
circuit
I/O1 7
26
I/O6
CE
V 8
25
CC GND
GND 9 24 V
CC
I/O2 10 23 I/O5
22 I/O4
I/O3 11
21 A12
WE 12
20 A11
A4 13
19 A10
A5 14
A6 15 18 A9
A7 16
17 A8
9/20/06, v. 1.0 Alliance Memory P. 1 of 9
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Address decoder
A9
A10
A11
A12
A13
A14
A15
A16
Sense amp
AS7C31025C AS7C31025CAS7C31025C
Functional description
The AS7C31025C is 3V a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x
8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t , t , t ) of 10 ns with output enable access times (t ) of 5 ns are ideal for high-performance
AA RC WC OE
applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025C is packaged in common
industry standard packages.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V relative to GND V 0.50 +4.6 V
CC t1
Voltage on any pin relative to GND V 0.50 V + 0.5 V
t2 CC
Power dissipation P 1.25 W
D
o
Storage temperature (plastic) T 55 +125 C
stg
o
Ambient temperature with V applied T 55 +125 C
CC bias
DC current into outputs (low) I 50 mA
OUT
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE WE OE Data Mode
H X X High Z Standby (I , I )
SB SB1
L H H High Z Output disable (I )
CC
LHL D Read (I )
OUT CC
LL X D Write (I )
IN CC
Key: X = dont care, L = low, H = high.
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