September 2006 AS7C31026C Advance Information 3.3 V 64K X 16 CMOS SRAM Features o o JEDEC standard packaging Industrial (-40 to 85 C) temperature - 44-pin 400 mil SOJ Organization: 65,536 words 16 bits - 44-pin TSOP 2-400 Center power and ground pins for low noise - 48-ball 7 7 mm BGA High speed ESD protection 2000 volts - 12 ns address access time - 6 ns output enable access time Low power consumption via chip deselect Upper and Lower byte pin Easy memory expansion with CE, OE inputs TTL-compatible, three-state I/O Logic block diagram Pin arrangement A0 A1 V 44-Pin SOJ (400 mil), TSOP 2 CC A2 65,536 16 GND A3 Array 1 44 A5 A4 A4 2 43 A6 A3 A5 A2 3 42 A7 4 41 OE A1 A6 5 40 UB A0 A7 6 39 LB CE I/O0 7 38 I/O15 I/O0I/O7 I/O 8 37 I/O14 I/O1 Control circuit buffer I/O8I/O15 9 36 I/O13 I/O2 I/O3 10 35 I/O12 V 11 34 GND CC Address decoder WE 12 33 V GND CC 13 32 I/O11 I/O4 I/O5 14 31 I/O10 15 30 I/O9 I/O6 16 29 I/O8 I/O7 UB 17 28 NC WE A15 18 27 A8 OE 19 26 A9 A14 20 25 A10 LB A13 A12 21 24 A11 CE NC 22 23 NC 0000048 - BGA Ball-Grid-Array Package 1 2 3 4 5 6 A LB OE A A A NC 0 1 2 B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D V I/O11 NC A7 I/O3 V SS DD E V I/O12 NC NC I/O4 V DD SS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 9/20/06, v 2.0 Alliance Memory P. 1 of 10 Copyright Alliance Memory. All rights reserved. Address decoder A8 A9 A10 A11 A12 A13 A14 A15 AS 7C 31 02 6CAS7C31026C Functional description The AS7C31026C is a 3V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 12 ns with output enable access times (t ) of 6 ns are ideal for high- AA RC WC OE performance applications. When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31026C is packaged in . common industry standard packages Absolute maximum ratings Parameter Symbol Min Max Unit relative to GND V 0.50 +4.60 V Voltage on V CC t1 Voltage on any pin relative to GND V 0.50 V +0.50 V t2 CC Power dissipation P 1.25 W D Storage temperature (plastic) T 55 +125 C stg Ambient temperature with VCC applied T 55 +125 C bias DC current into outputs (low) I 50 mA OUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0I/O7 I/O8I/O15 Mode H X X X X High Z High Z Standby (I ), I ) SB SBI L H L L H D High Z Read I/O0I/O7 (I ) OUT CC L H L H L High Z D Read I/O8I/O15 (I OUT CC) L H L L L D D Read I/O0I/O15 (I ) OUT OUT CC L L X L L D D Write I/O0I/O15 (I ) IN IN CC L L X L H D High Z Write I/O0I/O7 (I ) IN CC L L X H L High Z D Write I/O8I/O15 (I ) IN CC L H H X X High Z High Z Output disable (I ) CC L X X H H Key: H = high, L = low, X = dont care. 9/20/06, v 2.0 Alliance Memory P. 2 of 10