February 2006 AS7C32096A 3.3V 256K 8 CMOS SRAM Features Equal access and cycle times Industrial and commercial temperature Easy memory expansion with CE, OE inputs Organization: 262,144 words 8 bits TTL-compatible, three-state I/O Center power and ground pins JEDEC standard packages High speed - 44-pin TSOP 2 - 10/12/15/20 ns address access time ESD protection 2000 volts - 4/5/6/7 ns output enable access time Latch-up current 200 mA Low power consumption: ACTIVE - 650 mW / max 10 ns Low power consumption: STANDBY - 28.8 mW / max CMOS Logic block diagram Pin arrangements 44-pin TSOP 2 V NC NC CC 1 44 NC NC 2 43 GND NC A0 3 42 Input buffer A17 A1 4 41 A2 A16 5 40 A0 A3 A15 6 39 A1 I/O1 A4 7 38 A14 A2 262,144 8 A3 CE 8 37 OE A4 I/O1 9 36 I/O8 Array A5 I/O2 I/O7 10 35 (2,097,152) A6 V 11 34 GND A7 CC I/O8 V A8 GND 12 33 CC A9 I/O3 13 32 I/O6 I/O4 14 31 I/O5 Column decoder WE Control WE 15 30 A13 OE Circuit A5 16 29 A12 CE A6 17 28 A11 A7 18 27 A10 A8 NC 19 26 A9 NC 20 25 NC NC 21 24 NC NC 22 23 Selection guide 10 12 15 20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 4 5 6 7 ns Industrial 180 160 140 110 mA Maximum operating current Commercial 170 150 130 100 mA Maximum CMOS standby current 8 8 8 8 mA 2/17/06, v 1.1 Alliance Semiconductor P. 1 of 9 Copyright Alliance Semiconductor. All rights reserved. Row decoder A10 A11 A12 A13 A14 A15 A16 A17 Sense ampAS7C32096A Functional description The AS7C32096A is a high-performance CMOS 2,097,152-bit Static Random Access Memory (SRAM) device organized as 262,144 words 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 4/5/6/7 ns are AA RC WC OE ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1I/O8 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. This device is available as per industry standard 44-pin TSOP 2 package. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.5 +5.0 V CC t1 Voltage on any pin relative to GND V 0.5 V +0.5 V t2 CC Power dissipation P 1.0 W D Storage temperature (plastic) T 65 +150 C stg Temperature with V applied T 55 +125 C CC bias DC current into output (low) I 20 mA OUT NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (I , I ) SB SB1 L H H High Z Output disable (I ) CC LHL D Read (I ) OUT CC LL X D Write (I ) IN CC Key: X = Dont care, L = Low, H = High 2/17/06, v 1.1 Alliance Semiconductor P. 2 of 9