February 2006 AS7C4096A 5.0V 512K 8 CMOS SRAM Equal access and cycle times Features CE, OE inputs Easy memory expansion with Pin compatible to AS7C4096 TTL-compatible, three-state I/O Industrial and commercial temperature JEDEC standard packages Organization: 524,288 words 8 bits - 400 mil 36-pin SOJ Center power and ground pins - 44-pin TSOP 2 High speed ESD protection 2000 volts - 10/12/15/20 ns address access time Latch-up current 200 mA - 5/6 ns output enable access time Low power consumption: ACTIVE - 880mW/max 10 ns Low power consumption: STANDBY - 55mW/max CMOS Logic block diagram Pin arrangements 36-pin SOJ (400 mil) 44-pin TSOP 2 V CC NC NC 1 44 A0 1 36 NC NC NC 2 43 GND A1 2 35 A18 NC A0 3 42 A2 3 34 A17 A18 A1 4 41 Input buffer A3 4 33 A16 A2 5 40 A17 A4 5 32 A15 A3 A16 6 39 CE 6 31 OE A4 7 38 A15 A0 I/O1 7 30 I/O8 CE 8 37 OE A1 I/O2 8 29 I/O7 I/O1 I/O8 9 36 I/O1 V 9 28 GND A2 CC I/O2 10 35 I/O7 V GND 10 27 524,288 8 CC V A3 11 34 GND CC I/O3 11 26 I/O6 V GND 12 33 CC A4 Array I/O4 12 25 I/O5 I/O3 13 32 I/O6 A5 WE 13 24 A14 I/O4 14 31 I/O5 (4,194,304) A6 A5 14 23 A13 WE 15 30 A14 A7 A6 15 22 A12 A5 A13 16 29 I/O8 A8 A7 16 21 A11 A6 17 28 A12 A8 17 20 A10 A7 A11 18 27 A9 A9 18 19 NC A8 19 26 A10 NC A9 20 25 Column decoder NC NC WE 21 24 Control NC 22 23 NC OE Circuit CE Selection guide 10 12 15 20 Unit Maximum address access time 10 12 15 20 ns Maximum outputenable access time 5 6 6 6 ns Maximum operating current 160 140 120 100 mA Maximum CMOS standby current 10 10 10 10 mA 2/21/06, v 1.2 Alliance Semiconductor P. 1 of 10 Copyright Alliance Semiconductor. All rights reserved. Row decoder A10 A11 A12 A13 A14 A15 A16 A17 A18 Sense ampAS7C4096A Functional description The AS7C4096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5/6 ns are ideal AA RC WC OE for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1I/O8 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5.0V supply voltage. This device is available as per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on V relative to GND V 0.5 +7.0 V CC t1 Voltage on any pin relative to GND V 0.5 V +0.5 V t2 CC Power dissipation P 1.0 W D Storage temperature (plastic) T 65 +150 C stg Temperature with V applied T 55 +125 C CC bias DC current into output (low) I 20 mA OUT NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode Standby (I , I ) H X X High Z SB SB1 Output disable (I ) L H H High Z CC D Read (I ) LH L OUT CC D Write (I ) LL X IN CC 2/21/06, v 1.2 Alliance Semiconductor P. 2 of 10