128K x 36, 256K x 18 AS8C403600 3.3V Synchronous SRAMs AS8C401800 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Features Description 128K x 36, 256K x 18 memory configurations TheAS8C403600/1800 are high- speed SRAMs organized as Supports high system speed: 128K x 36/256K x 18. TheAS8C403600/401800 SRAMs contain write, Commercial: data, address and control registers. Internal logic allows the SRAM to 150MHz 3.8ns clock access time generate a self-timed write based upon a decision which can be left until the end of the write cycle. LBO input selects interleaved or linear burst mode The burst mode feature offers the highest level of performance to the Self-timed write cycle with global write control ( l ( GW), byte system designer,as the AS8C403600/1800 can provide four cycles of data write enable (BWE), and byte writes (BWx) for a single address presented to the SRAM. An internal burst address 3.3V core power supply counter accepts the first cycle address from the processor, initiating the Power down controlled by ZZ input access sequence. The first cycle of output data will be pipelined for one 3.3V I/O cycle before it is available on the next rising clock edge. If burst mode Optional - Boundary Scan JTAG Interface (IEEE 1149.1 operation is selected (( ADV=LOW), the subsequent three cycles of output compliant) data will be available to the user on the next three rising clock edges. The Packaged in a JEDEC Standard 100-pin plastic thin quad order of these three addresses are defined by the internal burst counter flatpack (TQFP). and the LBO input pin. The AS8C403600/1800 SRAMs utilize the latest high- performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP). Pin Description Summary A0-A17 Address Inputs Input Synchronous Chip Enable Input Synchronous CE CS0, CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous Global Write Enable Input Synchronous GW BWE Byte Write Enable Input Synchronous (1) Individual Byte Write Selects Input Synchronous BW1, BW2, BW3, BW4 CLK Clock Input N/A Burst Address Advance Input Synchronous ADV Address Status (Cache Controller) Input Synchronous ADSC Address Status (Processor) Input Synchronous ADSP LBO Linear / Interleaved Burst Order Input DC TMS Test Mode Select Input Synchronous TDI Test Data Input Input Synchronous TCK Test Clock Input N/A TDO Test Data Output Output Synchronous ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A NOTE: 1. BW3 and BW4 are not applicable for the AS8C401800. September 2010 1 DSC-5279/05AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range (1) Pin Definitions Symbol Pin Function I/O Active Description Synchronous Address inputs. The address register is triggered by a combination of the rising edge A0-A17 Address Inputs I N/A of CLK and ADSC Lo w o r ADSP Low and CE Lo w. Address Status Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load ILOW ADSC (Cache Controller) the address registers with new addresses. Address Status Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the ADSP ILOW (Processor) address registers with new addresses. ADSP is gated by CE. Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal Burst Address ADV ILOW burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the Advance burst c ounter is not incremented that is, there is no address advance. Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising BWE Byte Write Enable I LOW edge of CLK then BWx inputs are p assed to the next stage in the circuit.BW If E is HIGH then the byte write inputs are blocked and only GW can initiate a w rite cycle. Individual Byte 1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any Synchronous byte write enables. BW BW1-BW4 ILOW Write Enables active byte write causes all outputs to be disabled. Synchronous chip enable. CE is used with CS0 and CS1 to enable the AS8C403600/1800. CE also g ates Chip Enable I LOW CE ADSP. CLK Clock I N/A This is the clock input. All timing references fo r the device are made with respect to this input. CS0 Chip Select 0 I HIGH Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip. CS1 Chip Select 1 I LOW Synchronous active LOW chip select.CS 1 is used with CE and CS0 to e nable the chip. Global Write Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising GW ILOW Enable edge of CLK. GW supersedes individual byte write enables. I/O0-I/O31 Synchronous d ata input/output (I/O) p ins. Both the data input path and d ata output path are registered Data Input/Output I/O N/A I/OP1-I/OP4 and triggered by the rising edge of CLK. Asynchronous burst order selection input. WhenLBO is HIGH, the interleaved burst sequence is LBO Linear Burst Order I LOW selected. When LBO is LOW the Linear burst sequence is selected. LBO is a s tatic input and must not change state while the device is operating. Asynchronous output enable. WhenOE is LOW the data output drivers are enabled on the I/O pins if Output Enable I LOW OE the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state. Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal TMS Test ModeSelect I N/A pullup. Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has TDI Test Data Input I N/A an internal pullup. Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK Test Clock I N/A TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup. Serial output of registers placed between TDI and TDO. This output is active depending on the state TDO Test DataOutput O N/A of the TAP controller. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the ZZ Sleep Mode I HIGH AS8C403600/1800 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull down. DD Power Supply N/A N/A 3.3V c ore power supply. V VDDQ Power Supply N/A N/A 3.3V I/O Supply. VSS Ground N/A N/A Ground. NC No Connect N/A N/A NC pins are not e lectrically connected to the d evice. 5279 tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.422