2.5 V to 5.5 V, 500 A, Parallel Interface a Quad Voltage-Output 8-/10-/12-Bit DACs AD5334/AD5335/AD5336/AD5344* FEATURES GENERAL DESCRIPTION AD5334: Quad 8-Bit DAC in 24-Lead TSSOP The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and AD5335: Quad 10-Bit DAC in 24-Lead TSSOP 12-bit DACs. They operate from a 2.5 V to 5.5 V supply con- AD5336: Quad 10-Bit DAC in 28-Lead TSSOP suming just 500 A at 3 V, and feature a power-down mode that AD5344: Quad 12-Bit DAC in 28-Lead TSSOP further reduces the current to 80 nA. These devices incorporate Low Power Operation: 500 A 3 V, 600 A 5 V an on-chip output buffer that can drive the output to both sup- Power-Down to 80 nA 3 V, 200 nA 5 V via PD Pin ply rails. 2.5 V to 5.5 V Power Supply The AD5334/AD5335/AD5336/AD5344 have a parallel interface. Double-Buffered Input Logic CS selects the device and data is loaded into the input registers Guaranteed Monotonic by Design Over All Codes on the rising edge of WR. Output Range: 0V or 02 V REF REF Power-On Reset to Zero Volts The GAIN pin on the AD5334 and AD5336 allows the output Simultaneous Update of DAC Outputs via LDAC Pin range to be set at 0 V to V or 0 V to 2 V . REF REF Asynchronous CLR Facility Input data to the DACs is double-buffered, allowing simultaneous Low Power Parallel Data Interface update of multiple DACs in a system using the LDAC pin. On-Chip Rail-to-Rail Output Buffer Ampliers On the AD5334, AD5335 and AD5336 an asynchronous CLR Temperature Range: 40 C to +105 C input is also provided. This resets the contents of the Input APPLICATIONS Register and the DAC Register to all zeros. These devices also Portable Battery-Powered Instruments incorporate a power-on-reset circuit that ensures that the DAC Digital Gain and Offset Adjustment output powers on to 0 V and remains there until valid data is Programmable Voltage and Current Sources written to the device. Programmable Attenuators The AD5334/AD5335/AD5336/AD5344 are available in Thin Industrial Process Control Shrink Small Outline Packages (TSSOP). AD5334 FUNCTIONAL BLOCK DIAGRAM (Other Diagrams Inside) V A/B V REF DD POWER-ON AD5334 RESET GAIN DAC INPUT DB 7 8-BIT . BUFFER V A REGISTER REGISTER OUT . DAC . DB 0 CS INPUT DAC 8-BIT BUFFER V B REGISTER REGISTER OUT DAC WR INTER- FACE A0 LOGIC DAC INPUT 8-BIT 8-BIT A1 BUFFER REGISTER V C REGISTER OUT DAC DAC INPUT DAC 8-BIT BUFFER V D OUT REGISTER REGISTER DAC TO ALL DACS CLR AND BUFFERS LDAC POWER-DOWN LOGIC V C/D PD GND REF *Protected by U.S. Patent Number 5,969,657 . REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD5334/AD5335/AD5336/AD5344SPECIFICATIONS (V = 2.5 V to 5.5 V, V = 2 V. R = 2 k to GND C =200 pF to GND all specications T to T unless otherwise noted.) DD REF L L MIN MAX 2 B Version 1 Parameter Min Typ Max Unit Conditions/Comments 3, 4 DC PERFORMANCE AD5334 Resolution 8 Bits Relative Accuracy 0.15 1 LSB Differential Nonlinearity 0.02 0.25 LSB Guaranteed Monotonic By Design Over All Codes AD5335/AD5336 Resolution 10 Bits Relative Accuracy 0.5 4 LSB Differential Nonlinearity 0.05 0.5 LSB Guaranteed Monotonic By Design Over All Codes AD5344 Resolution 12 Bits Relative Accuracy 2 16 LSB Differential Nonlinearity 0.2 1 LSB Guaranteed Monotonic By Design Over All Codes Offset Error 0.4 3 % of FSR Gain Error 0.1 1 % of FSR 5 Lower Deadband 10 60 mV Lower Deadband Exists Only if Offset Error Is Negative Upper Deadband 10 60 mV V = 5 V. Upper Deadband Exists Only if V V DD REF = DD 6 Offset Error Drift 12 ppm of FSR/C 6 Gain Error Drift 5 ppm of FSR/C 6 DC Power Supply Rejection Ratio 60 dB V = 10% DD 6 DC Crosstalk 200 VR = 2 k to GND, 2 k to V C = 200 pF to GND L DD L Gain = 0 6 DAC REFERENCE INPUT V Input Range 0.25 V V REF DD V Input Impedance 180 k Gain = 1. Input Impedance = R (AD5336/AD5344) REF DAC 90 k Gain = 2. Input Impedance = R (AD5336) DAC 90 k Gain = 1. Input Impedance = R (AD5334/AD5335) DAC 45 k Gain = 2. Input Impedance = R (AD5334) DAC Reference Feedthrough 90 dB Frequency = 10 kHz Channel-to-Channel Isolation 90 dB Frequency = 10 kHz 6 OUTPUT CHARACTERISTICS 4, 7 Minimum Output Voltage 0.001 V min Rail-to-Rail Operation 4, 7 Maximum Output Voltage V 0.001 V max DD DC Output Impedance 0.5 Short Circuit Current 50 mA V = 5 V DD 20 mA V = 3 V DD Power-Up Time 2.5 s Coming Out of Power-Down Mode. V = 5 V DD 5 s Coming Out of Power-Down Mode. V = 3 V DD 6 LOGIC INPUTS Input Current 1 A V , Input Low Voltage 0.8 V V = 5 V 10% IL DD 0.6 V V = 3 V 10% DD 0.5 V V = 2.5 V DD V , Input High Voltage 2.4 V V = 5 V 10% IH DD 2.1 V V = 3 V 10% DD 2.0 V V = 2.5 V DD Pin Capacitance 3.5 pF POWER REQUIREMENTS V 2.5 5.5 V DD I (Normal Mode) All DACs active and excluding load currents. DD V = 4.5 V to 5.5 V 600 900 AV = V , V = GND. DD IH DD IL V = 2.5 V to 3.6 V 500 700 AI increases by 50 A at V > V 100 mV. DD DD REF DD I (Power-Down Mode) DD V = 4.5 V to 5.5 V 0.2 1 A DD V = 2.5 V to 3.6 V 0.08 1 A DD NOTES 1 See Terminology section. 2 Temperature range: B Version: 40C to +105C typical specications are at 25C. 3 Linearity is tested using a reduced code range: AD5334 (Code 8 to 255) AD5335/AD5336 (Code 28 to 1023) AD5344 (Code 115 to 4095). 4 DC specications tested with outputs unloaded. 5 This corresponds to x codes. x = Deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 In order for the amplier output to reach its minimum voltage, Offset Error must be negative. In order for the amplier output to reach its maximum voltage, V = V and REF DD Offset plus Gain Error must be positive. Specications subject to change without notice. 2 REV. 0