8-Bit, High Bandwidth Multiplying DAC with Serial Interface Data Sheet AD5425 FEATURES GENERAL DESCRIPTION 1 2.5 V to 5.5 V supply operation The AD5425 is a CMOS, 8-bit, current output digital-to-analog 50 MHz serial interface converter (DAC) that operates from a 2.5 V to 5.5 V power supply, 2.47 MSPS update rate making it suitable for battery-powered applications and many INL of 0.25 LSB other applications. 10 MHz multiplying bandwidth This DAC utilizes a double buffered, 3-wire serial interface that 10 V reference input is compatible with SPI, QSPI, MICROWIRE, and most DSP Low glitch energy: <2 nV-s interface standards. An pin is also provided, which Extended temperature range: 40C to +125C LDAC 10-lead MSOP package allows simultaneous updates in a multiDAC configuration. On Guaranteed monotonic power-up, the internal shift register and latches are filled with 4-quadrant multiplication 0s and the DAC outputs are 0 V. Power-on reset with brownout detection As a result of manufacturing on a CMOS submicron process, function LDAC this DAC offers excellent 4-quadrant multiplication charac- 0.4 A typical power consumption teristics with large signal multiplying bandwidths of 10 MHz. APPLICATIONS The applied external reference input voltage (V ) determines REF Portable battery-powered applications the full-scale output current. An integrated feedback resistor, Waveform generators RFB, provides temperature tracking and full-scale voltage output Analog processing Instrumentation applications when combined with an external I to V precision amplifier. Programmable amplifiers and attenuators The AD5425 is available in a small, 10-lead MSOP package. Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM V V DD REF R AD5425 R FB I 1 8-BIT OUT R-2R DAC I 2 OUT LDAC DAC REGISTER POWER-ON RESET INPUT LATCH SYNC CONTROL LOGIC AND SCLK INPUT SHIFT REGISTER SDIN GND Figure 1. 1 U.S. Patent No. 5,969,657. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 03161-001AD5425 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Operation ....................................................................... 14 Applications ....................................................................................... 1 Single-Supply Applications ....................................................... 15 General Description ......................................................................... 1 Adding Gain ................................................................................ 16 Functional Block Diagram .............................................................. 1 DACs Used as a Divider or Programmable Gain Element ... 16 Revision History ............................................................................... 2 Reference Selection .................................................................... 16 Specifications ..................................................................................... 3 Amplifier Selection .................................................................... 17 Timing Characteristics ..................................................................... 5 Serial Interface ............................................................................ 19 Absolute Maximum Ratings ............................................................ 6 Microprocessor Interfacing ....................................................... 19 ESD Caution .................................................................................. 6 PCB Layout and Power Supply Decoupling ................................ 22 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 23 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 23 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 14 REVISION HISTORY 1/16Rev. C to Rev. D 6/12Rev. A to Rev. B Deleted Positive Output Voltage Section ........................................ 16 Deleted ADSP-2103 and changed ADSP-2191 to Changes to Adding Gain Section .................................................... 16 ADSP-2191M Throughout ............................................................ 19 Changes to ADSP-21xx to AD5425 Interface Section Deleted Evaluation Board Section and Operating the Evaluation and Figure 39 .................................................................................... 19 Board Section, deleted Figure 46 to Figure 49, and deleted Changes to ADSP-BF504 to ADSP-BF592 Device Family to Table 11 ............................................................................................ 23 AD5425 Interface Section, MC68HC11 Interface to AD5425 Changes to Ordering Guide .......................................................... 23 Interface Section, and Figure 40 and Figure 41 Captions ......... 20 3/05Rev. 0 to Rev. A Changes to PIC16C6x/PIC16C7x to AD5425 Section .............. 21 Updated Format .................................................................. Universal Changes to Specifications Section ................................................... 3 9/12Rev. B to Rev. C Added Figure 18, Figure 20, Figure 21 ........................................ 10 Change to Features ........................................................................... 1 Change to Table 7 ........................................................................... 18 2/04Revision 0: Initial Version Rev. D Page 2 of 24