8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface Data Sheet AD5426/AD5432/AD5443 FEATURES GENERAL DESCRIPTION 1 2.5 V to 5.5 V supply operation The AD5426/AD5432/AD5443 are CMOS 8-, 10-, and 12-bit 50 MHz serial interface current output digital-to-analog converters (DACs), respectively. 10 MHz multiplying bandwidth These devices operate from a 2.5 V to 5.5 V power supply, 2.5 MSPS update rate making them suitable for battery-powered applications and INL of 1 LSB for 12-bit DAC many other applications. 10 V reference input These DACs use a double buffered, 3-wire serial interface that is Low glitch energy < 2 nV-s compatible with SPI, QSPI, MICROWIRE, and most DSP Extended temperature range 40C to +125C interface standards. In addition, a serial data out pin (SDO) 10-lead MSOP allows for daisy-chaining when multiple packages are used. Pin-compatible 8-, 10-, and 12-bit current output DACs Data readback allows the user to read the contents of the DAC Guaranteed monotonic register via the SDO pin. On power-up, the internal shift register 4-quadrant multiplication and latches are filled with 0s and the DAC outputs are at zero scale. Power-on reset with brownout detection As a result of manufacturing on a CMOS submicron process, Daisy-chain mode the parts offer excellent 4-quadrant multiplication characteristics Readback function with large signal multiplying bandwidths of 10 MHz. The applied 0.4 A typical power consumption external reference input voltage, V , determines the full-scale REF APPLICATIONS output current. An integrated feedback resistor, RFB, provides Portable battery-powered applications temperature tracking and full-scale voltage output when combined Waveform generators with an external current to voltage precision amplifier. Analog processing The AD5426/AD5432/AD5443 DACs are available in small, Instrumentation 10-lead MSOPs. Programmable amplifiers and attenuators The EV-AD5443/46/53SDZ evaluation board is available for Digitally controlled calibration evaluating DAC performance. For more information, see the Programmable filters and oscillators UG-327 evaluation board user guide. Composite video Ultrasound Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM V V DD REF R AD5426/ R FB AD5432/ I 1 8-/10-/12-BIT OUT AD5443 R-2R DAC I 2 OUT DAC REGISTER POWER-ON RESET INPUT LATCH SYNC CONTROL LOGIC AND SCLK INPUT SHIFT REGISTER SDIN SDO GND Figure 1. 1 Protected by U.S. Patent No. 5,689,257. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 03162-001AD5426/AD5432/AD5443 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Operation ....................................................................... 15 Applications ....................................................................................... 1 Single-Supply Applications ....................................................... 17 General Description ......................................................................... 1 Adding Gain ................................................................................ 17 Functional Block Diagram .............................................................. 1 DACs Used as a Divider or Programmable Gain Element ... 18 Revision History ............................................................................... 2 Reference Selection .................................................................... 18 Specifications ..................................................................................... 3 Amplifier Selection .................................................................... 18 Timing Characteristics ................................................................ 5 Serial Interface ............................................................................ 20 Absolute Maximum Ratings ............................................................ 6 PCB Layout and Power Supply Decoupling ................................ 22 ESD Caution .................................................................................. 6 Overview of the AD5426/AD5432/AD5443 and Related DACs .. 23 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 24 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 24 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 REVISION HISTORY 9/15Rev. G to Rev. H Deleted 80C51/80L51 to AD5426/AD5432/AD5443 Interface Deleted Positive Output Voltage Section and Figure 45 Section, Figure 55, MC68HC11 Interface to AD5426/AD5432/ Renumbered Sequentially .............................................................. 17 AD5443 Interface Section, Figure 56, MICROWIRE to Changes to Adding Gain Section ................................................. 17 AD5426/AD5432/AD5443 Interface Section, Figure 57, Changed Overview of AD54xx and AD55xx Devices Section PIC16C6x/7x to AD5426/AD5432/AD5443, and Figure 58 .... 22 to Overview of the AD5426/AD5432/AD5443 and Related Deleted Evaluation Board for the AD5426/AD5432/AD5443 DACs Section .................................................................................. 23 Series of DACs Section, Operating the Evaluation Board Changes to Ordering Guide .......................................................... 24 Section, and Power Supplies Section ........................................... 23 Deleted Figure 59 and Figure 60................................................... 24 6/13Rev. F to Rev. G Updated Outline Dimensions ....................................................... 24 Change to General Description Section ........................................ 1 Changes to Ordering Guide .......................................................... 24 Changes to Ordering Guide .......................................................... 24 Deleted Figure 61 ............................................................................ 25 Deleted Figure 62 ............................................................................ 26 7/12Rev. E to Rev. F No Change to Content, Changed VDD Values in 7/12 Revision 2/09Rev. B to Rev. C History Only ...................................................................................... 2 Changes to Low Power Serial Interface Section and Daisy- Chain Mode Section ....................................................................... 20 7/12Rev. D to Rev. E Updated Outline Dimensions ....................................................... 28 Changed V = 3 V to V = 2.5 V ............................. Throughout DD DD Changes to Table 2 ............................................................................ 4 11/08Rev. A to Rev. B Changes to Table 4 ............................................................................ 7 Changes to Ordering Guide .......................................................... 28 Change to Daisy-Chain Mode Section ........................................ 20 Change to Ordering Guide ............................................................ 24 5/05Rev. 0 to Rev. A Updated Format .................................................................. Universal 4/12Rev. C to Rev. D Changes to Specifications ................................................................. 3 Changed V = 2.5 V to V = 3 V ............................. Throughout Changes to Figure 42 ...................................................................... 16 DD DD Changes to General Description Section ...................................... 1 Change to Figure 45 ....................................................................... 17 Deleted Microprocessor Interface Section, ADSP-21xx to Change to Figure 46 ....................................................................... 18 Changes to Table 7, Table 8, and Table 9 ..................................... 19 AD5426/AD5432/AD5443 Interface Section, Figure 51, Figure 52, Table 11, ADSP-BF5x to AD5426/AD5432/AD5443 Additions to Microprocessor Interface Section.......................... 21 Interface Section, Figure 53 and Figure 54 Renumbered Sequentially ..................................................................................... 21 2/04Revision 0: Initial Version Rev. H Page 2 of 24