Monolithic, 12-Bit Quad DAC Data Sheet AD664 The analog portion of the AD664 consists of four DAC cells, FEATURES four output amplifiers, a control amplifier, and switches. Each Four complete voltage-output DACs DAC cell is an inverting R-2R type. The output current from Data register readback feature each DAC is switched to the on-board application resistors Reset to zero override and output amplifier. The output range of each DAC cell is Multiplying operation programmed through the digital input/output port and may be Double buffered latches set to unipolar (UNI) or bipolar (BIP) range, with a gain of one Surface-mount (LCC, PLCC, and JLCC) and PDIP and SBDIP or two times the reference voltage. All DACs are operated from packages a single external reference. MIL-STD-883 compliant versions available The functional completeness of the AD664 results from the APPLICATIONS combination of the Analog Devices, Inc., BiMOS II process, laser Automatic test equipment trimmed thin film resistors, and double level metal interconnects. Robotics PRODUCT HIGHLIGHTS Process control Disk drives 1. The AD664 provides four voltage-output DACs on one Instrumentation chip offering the highest density 12-bit DAC function Avionics available. 2. The output range of each DAC is fully and independently GENERAL DESCRIPTION programmable. The AD664 is four complete 12-bit, voltage-output digital-to- 3. Readback capability allows verification of contents of the analog converters (DACs) on one monolithic IC chip. Each internal data registers. DAC has a double buffered input latch structure and a data 4. The asynchronous reset control returns all DAC outputs to readback function. All DAC read and write operations occur 0 V. through a single microprocessor-compatible input/output (I/O) 5. DAC to DAC matching performance is specified and port. tested. 6. Linearity error is specified to be 1/2 LSB at room The I/O port accommodates 4-bit, 8-bit, or 12-bit parallel words temperature and 3/4 LSB maximum for the K, B, and T allowing simple interfacing with a wide variety of grades. microprocessors. A reset to zero control pin is provided to allow 7. DAC performance is guaranteed to be monotonic over the a user to simultaneously reset all DAC outputs to zero, regardless full operating temperature range. of the contents of the input latch. Any one or all of the DACs 8. Readback buffers have tristate outputs. may be placed in a transparent mode allowing immediate 9. Multiplying mode operation allows use with fixed, variable, response by the outputs to the input data. positive, or negative external references. 10. The AD664 is available in versions compliant with MILSTD-883. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AD664 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Update Second Rank of a DAC ................................................ 19 Applications ....................................................................................... 1 Preload Multiple First Rank Registers ..................................... 19 General Description ......................................................................... 1 Load and Update Multiple DAC Outputs ............................... 19 Product Highlights ........................................................................... 1 Selecting Gain Range and Modes (44-Lead Versions (JLCC and PLCC) and 44-Terminal Version (LCC)) ........................ 19 Revision History ............................................................................... 2 Load and Update Mode of One DAC ...................................... 20 Functional Block Diagrams ............................................................. 4 Preloading the Mode Select Register ....................................... 21 Specif icat ions ..................................................................................... 5 Transparent Operation (44-Lead Versions (JLCC and PLCC) Absolute Maximum Ratings ............................................................ 8 and 44-Terminal Version (LCC)) ............................................. 22 ESD Caution .................................................................................. 8 Output Data..................................................................................... 23 Pin Configurations and Function Descriptions ........................... 9 DAC Data Readback .................................................................. 23 Terminology .................................................................................... 12 Mode Data Readback ................................................................. 23 Theory of Operation ...................................................................... 13 Output Loads .............................................................................. 24 44-Lead (JLCC/PLCC) Version and 44-Terminal (LCC) Asynchronous Reset Operation ............................................... 24 Version ......................................................................................... 13 Interfacing the AD664 to Microprocessors ................................ 25 28-Lead Versions ........................................................................ 13 MC6801 Interface ....................................................................... 25 Analog Circuit Considerations ..................................................... 14 8051 Interface.............................................................................. 27 Grounding Recommendations ................................................. 14 IBM PC Interface ........................................................................ 28 Power Supplies and Decoupling ............................................... 14 Simple AD664 to MC68000 Interface ..................................... 31 Driving the Reference Input ..................................................... 14 Applications Information .............................................................. 32 Output Considerations .............................................................. 14 Tester per Pin Automatic Test Equipment (ATE) Multiplying Mode Performance ............................................... 15 Architecture ................................................................................ 32 Crosstalk ...................................................................................... 15 X-Axis and Y-Axis Plotters ....................................................... 33 Output Noise ............................................................................... 15 Die Information .............................................................................. 34 Digital Interface .............................................................................. 16 Outline Dimensions ....................................................................... 36 Input Data ........................................................................................ 17 Ordering Guide .......................................................................... 38 Timing Requirements .................................................................... 18 Load and Update One DAC Output ........................................ 18 Preloading the First Rank of One DAC ................................... 18 REVISION HISTORY 11/2018Rev. D to Rev. E Added Functional Block Diagrams Section ................................... 4 Updated Format .................................................................. Universal Changes to Figure 1 and Figure 2 .................................................... 4 Reorganized Layout ............................................................ Universal Changes to Specifications Section ................................................... 5 Changed 28-Pin to 28-Lead .............................................. Universal Changed Pin Configurations Section to Pin Configurations and Changed 44-Pin to 44-Lead and 44-Terminal ................ Universal Function Descriptions Section ........................................................ 9 Added 39-Pad Bare Die ..................................................... Universal Changes to Pin Configurations and Function Descriptions Removed AD345 ................................................................. Universal Section and Figure 3 .......................................................................... 9 Removed AD689 ................................................................. Universal Added Figure 4, Figure 5, and Table 3 Renumbered Changed Product Description Section to General Description Sequentially ........................................................................................ 9 Section ................................................................................................ 1 Changes to Figure 6 ........................................................................ 11 Deleted Pin Configurations Section .............................................. 1 Added Figure 7 and Table 4 .......................................................... 11 Changes to Product Highlights Section ......................................... 1 Changed Definitions of Specifications Section to Terminology Added Table of Contents Section ................................................... 2 S ection .............................................................................................. 12 Rev. E Page 2 of 39