3 V/5 V, Rail-to-Rail Quad, 8-Bit DAC AD7304/AD7305 FUNCTIONAL BLOCK DIAGRAMS FEATURES V V B V A Four 8-bit DACs in one package DD REF REF +3 V, +5 V, and 5 V operation 8 8 PWR-ON INPUT DAC A DAC A V A Rail-to-rail REF input to voltage output swing OUT RESET REG A REG 8 2.6 MHz reference multiplying bandwidth 8 8 INPUT DAC B V B DAC B OUT REG B REG Internal power-on reset SPI serial interface-compatibleAD7304 CS 8 8 INPUT DAC C DAC C V C OUT SERIAL REG C REG Fast parallel interfaceAD7305 SDI/SHDN REG 40 A power shutdown 8 8 INPUT CLK DAC D DAC D V D OUT REG D REG APPLICATIONS AD7304 Automotive output span voltage V GND V CV D SS CLR LDAC REF REF Instrumentation, digitally controlled calibration Figure 1. Pin-compatible AD7226 replacement when V < 5.5 V DD V V DD REF GENERAL DESCRIPTION 8 8 PWR-ON INPUT DAC A 1 V A DAC A The AD7304/AD7305 are quad, 8-bit DACs that operate from OUT RESET REG A REG DB0 8 a single +3 V to +5 V supply, or 5 V supplies. The AD7304 has 8 8 DB1 INPUT DAC B V B DAC B OUT REG B REG DB2 a serial interface, while the AD7305 has a parallel interface. DB3 Internal precision buffers swing rail-to-rail. The reference input DB4 8 8 INPUT DAC C DAC C V C DB5 REG C REG OUT range includes both supply rails, allowing for positive or negative DB6 8 8 8 INPUT DAC D full-scale output voltages. Operation is guaranteed over the DAC D V D OUT REG D REG WR supply voltage range of 2.7 V to 5.5 V, consuming less than A0/SHDN DECODE AD7305 A1 9 mW from a 3 V supply. V LDAC SS GND The full-scale voltage output is determined by the external Figure 2. reference input voltage applied. The rail-to-rail V input to REF DAC V allows for a full-scale voltage set equal to the positive OUT When operating from less than 5.5 V, the AD7305 is supply, VDD, the negative supply, VSS, or any value in between. pin-compatible with the popular industry-standard AD7226. The AD7304s doubled-buffered serial data interface offers high An internal power-on reset places both parts in the zero-scale speed, 3-wire, SPI-, and microcontroller-compatible inputs state at turn-on. A 40 A power shutdown (SHDN) feature is CS using data in (SDI), clock (CLK), and chip select ( ) pins. activated on both parts by three-stating the SDI/SHDN pin on Additionally, an internal power-on reset sets the output to zero the AD7304 and three-stating the A0/SHDN address pin on the scale. AD7305. The parallel input AD7305 uses a standard address decode The AD7304/AD7305 are specified over the extended industrial 40C to +85C and the automotive 40C to +125C along with the WR control line to load data into the input temperature ranges. AD7304s are available in a wide-body registers. 16-lead SOIC (R-16) package. The parallel input AD7305 is The double-buffered architecture allows all four input registers available in the wide-body 20-lead SOIC (R-20) surface-mount to be preloaded with new values, followed by an LDAC control package. For ultracompact applications, the thin 1.1 mm, strobe that copies all the new data into the DAC registers, 16-lead TSSOP (RU-16) package is available for the AD7304, thereby updating the analog output values. while the 20-lead TSSOP (RU-20) houses the AD7305. 1 Protected under Patent No. 5684481. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 2004 Analog Devices, Inc. All rights reserved. 01114-002 01114-001AD7304/AD7305 TABLE OF CONTENTS Specifications..................................................................................... 3 AD7304/AD7305 Power-On Reset .......................................... 15 Timing Specifications .................................................................. 4 Power up sequence..................................................................... 15 Absolute Maximum Ratings............................................................ 5 AD7305 Parallel Data Interface.................................................... 16 ESD Caution.................................................................................. 5 AD7226 Pin Compatibility ....................................................... 16 Pin Configurations and Function Descriptions ........................... 8 AD7305 Hardware Shutdown SHDN...................................... 16 Typical Performance Characteristics ........................................... 10 ESD Protection Circuits ............................................................ 16 Circuit Operation ........................................................................... 14 Applications..................................................................................... 17 DAC Section................................................................................ 14 Outline Dimensions ....................................................................... 18 AD7304 Serial Data Interface ....................................................... 15 Ordering Guide .......................................................................... 19 AD7304 Hardware Shutdown SHDN...................................... 15 Revision History 11/04Data Sheet Changed from Rev. B to Rev. C Update Format ....................................................................Universal Update Features ................................................................................ 1 Changes to Figure 35...................................................................... 15 Add Power-Up Sequence............................................................... 15 Changes to Figure 36...................................................................... 16 Change to Figure 37 ....................................................................... 16 Updated Outline Dimensions ....................................................... 18 2/04Data Sheet Changed from Rev. A to Rev. B Renumber TPCs and Figures ............................................Universal Deleted N-16 and N-20 packages.....................................Universal Changes to Absolute Maximum Ratings ....................................... 3 Changes to Ordering Guide ............................................................ 4 Updated Outline Dimensions ....................................................... 14 3/98Changed from Rev. 0 to Rev. A 2/98Revision 0: Initial Version Rev. C Page 2 of 20