CMOS 12-Bit a Buffered Multiplying DAC AD7545A FEATURES FUNCTIONAL BLOCK DIAGRAM Improved Version of AD7545 Fast Interface Timing All Grades 12-Bit Accurate 20-Lead DIP and Surface Mount Packages Low Cost GENERAL DESCRIPTION The AD7545A, a 12-bit CMOS multiplying DAC with internal data latches, is an improved version of the industry standard AD7545. This new design features a WR pulse width of 100 ns, which allows interfacing to a much wider range of fast 8-bit and 16-bit microprocessors. It is loaded by a single 12-bit-wide word under the control of the CS and WR inputs tying these control inputs low makes the input latches transparent, allowing unbuf- fered operation of the DAC. PIN CONFIGURATIONS DIP/SOIC LCCC PLCC REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD7545ASPECIFICATIONS (V = 10 V, V = O V, AGND = DGND unless otherwise noted) REF OUT1 V = +5 V V = +15 V DD DD Limits Limits 1 1 Parameter Version T = + 25 CT T T = + 25 CT T Units Test Conditions/Comments A MIN MAX A MIN MAX STATIC PERFORMANCE Resolution All 12 12 12 12 Bits Relative Accuracy K, B, T 1/2 1/2 1/2 1/2 LSB max L, C, U 1/2 1/2 1/2 1/2 LSB max Endpoint Measurement Differential Nonlinearity All 1 1 1 1 LSB max All Grades Guaranteed 12-Bit Monotonic Over Temperature Gain Error K, B, T 3 4 3 4 LSB max Measured Using Internal R . FB L, C, U 1 2 1 2 LSB max DAC Register Loaded with All 1s. 2 Gain Temperature Coefficient All 5 5 5 5 ppm/C max Gain/ Temperature All 2 2 2 2 ppm/C typ 2 DC Supply Rejection Gain/ V All 0.002 0.004 0.002 0.004 % per % max V = 5% DD DD Output Leakage Current at OUT1 K, L 10 50 10 50 nA max DB0DB11 = 0 V WR, CS = 0 V B, C 10 50 10 50 nA max T, U 10 200 10 200 nA max DYNAMIC PERFORMANCE 2 Current Settling Time All 1 1 1 1 s max To 1/2 LSB. OUT1 Load = 100 , C = 13 pF. DAC Output Measured EXT from Falling Edge of WR, CS = 0 V. 2 Propagation Delay (from Digital Input Change to 90% 3 of Final Analog Output) All 200 150 ns max OUT1 Load = 100 , C = 13 pF EXT Digital-to-Analog Glitch Impulse All 5 5 nV sec typ V = AGND. OUT1 Load = 100 , REF Alternately Loaded with All 0s and 1s. 2, 4 AC Feedthrough At OUT1 All 5 5 5 5 mV p-p typ V = 10 V, 10 kHz Sine Wave REF REFERENCE INPUT Input Resistance All 10 10 10 10 k min Input Resistance TC = 300 ppm/C typ (Pin 19 to GND) 20 20 20 20 k max Typical Input Resistance = 15 k ANALOG OUTPUTS 2 Output Capacitance C All 70 70 70 70 pF max DB0DB11 = 0 V, WR, CS = 0 V OUT1 C 150 150 150 150 pF max DB0DB11 = V , WR, CS = 0 V OUT1 DD DIGITAL INPUTS Input High Voltage V All 2.4 2.4 13.5 13.5 V min IH Input Low Voltage V All 0.8 0.8 1.5 1.5 V max IL 5 Input Current I All 1 10 1 10 A max V = 0 or V IN IN DD 2 Input Capacitance DB0DB11, WR, CS All 8 8 8 8 pF max 2 SWITCHING CHARACTERISTICS Chip Select to Write Setup Time K, B, L, C 100 130 75 85 ns min See Timing Diagram t T, U 100 170 75 95 ns min CS Chip Select to Write Hold Time t All 0 0 0 0 ns min CH Write Pulse Width K, B, L, C 100 130 75 85 ns min t t , T 0 CS WR CH t T, U 100 170 75 95 ns min WR Data Setup Time t All 100 150 60 80 ns min DS Data Hold Time t All 5 5 5 5 ns min DH POWER SUPPLY V All 5 5 15 15 V 5% For Specified Performance DD I All 2 2 2 2 mA max All Digital Inputs V or V DD IL IH 100 100 100 100 A max All Digital Inputs 0 V or V DD 10 10 10 10 A typ All Digital Inputs 0 V or V DD NOTES 1 Temperature range as follows: K, L Versions = 0C to +70C B, C Versions = 25C to +85C T, U Versions = 55C to +125C. 2 Sample tested to ensure compliance. 3 DB0DB11 = 0 V to V or V to 0 V. DD DD 4 Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND. 6 Logic inputs are MOS gates. Typical input current (+25C) is less than 1 nA. Specifications subject to change without notice. 2 REV. C