2 LC MOS Quad 14-Bit DACs AD7834/AD7835 into one via DIN, SCLK, and FSYNC. The AD7834 has five FEATURES dedicated package address pins, PA0 to PA4, that can be wired Four 14-bit DACs in one package to AGND or V to permit up to 32 AD7834s to be individually CC AD7834serial loading addressed in a multipackage application. AD7835parallel 8-bit/14-bit loading Voltage outputs The AD7835 can accept either 14-bit parallel loading or double- Power-on reset function byte loading, where right-justified data is loaded in one 8-bit Maximum/minimum output voltage range of 8.192 V byte and one 6-bit byte. Data is loaded from the external bus Maximum output voltage span of 14 V into one of the input latches under the control of the WR, CS, Common voltage reference inputs BYSHF, and DAC channel address pins, A0 to A2. User-assigned device addressing With each device, the LDAC signal is used to update all four Clear function to user-defined voltage DAC outputs simultaneously, or individually, on reception of Surface-mount packages CLR new data. In addition, for each device, the asynchronous AD783428-lead SOIC and PDIP input can be used to set all signal outputs, V 1 to V 4, to OUT OUT AD783544-lead MQFP and PLCC the user-defined voltage level on the device sense ground pin, APPLICATIONS DSG. On power-on, before the power supplies have stabilized, Process control internal circuitry holds the DAC output voltage levels to within Automatic test equipment 2 V of the DSG potential. As the supplies stabilize, the DAC General-purpose instrumentation output levels move to the exact DSG potential (assuming CLR is exercised). GENERAL DESCRIPTION The AD7834 is available in a 28-lead 0.3 SOIC package and a The AD7834 and AD7835 contain four 14-bit DACs on one 28-lead 0.6 PDIP package, and the AD7835 is available in a monolithic chip. The AD7834 and AD7835 have output 44-lead MQFP package and a 44-lead PLCC package. voltages in the range 8.192 V with a maximum span of 14 V. The AD7834 is a serial input device. Data is loaded in 16-bit format from the external serial bus, MSB first after two leading 0s, FUNCTIONAL BLOCK DIAGRAMS V V ()A V V V V () V (+) V V V (+)A CC DD SS REF REF CC DD SS REF REF DSGA AD7835 INPUT AD7834 INPUT DAC 1 DAC 1 DAC 1 REGISTER DAC 1 REGISTER LATCH LATCH BYSHF 1 PAEN 1 1 V 1 1 V 1 OUT OUT 14 DB13 INPUT PA0 INPUT INPUT DAC 2 BUFFER DAC 2 DB0 REGISTER DAC 2 REGISTER DAC 2 LATCH PA1 CONTROL LATCH 2 2 1 LOGIC V 2 OUT 1 V 2 OUT WR PA2 AND ADDRESS PA3 DECODE INPUT CS DAC 3 INPUT DAC 3 DAC 3 REGISTER PA4 LATCH REGISTER DAC 3 LATCH 3 3 1 V 3 OUT 1 V 3 OUT A0 FSYNC INPUT ADDRESS DAC 4 INPUT A1 REGISTER DAC 4 DAC 4 DECODE LATCH SERIAL-TO- REGISTER DAC 4 4 LATCH 1 DIN 4 V 4 PARALLEL A2 OUT 1 V 4 OUT CONVERTER CLR SCLK CLR AGND DGND V (+)B DSGB AGND DGND LDAC DSG LDAC V ()B REF REF Figure 1. AD7834 Figure 2. AD7835 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20032007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 01006-001 01006-002AD7834/AD7835 TABLE OF CONTENTS Power-On with CLR Low, LDAC High ................................... 17 Features .............................................................................................. 1 Power-On with LDAC Low, CLR High ................................... 17 Applications....................................................................................... 1 Loading the DAC and Using the CLR Input .......................... 17 General Description ......................................................................... 1 DSG Voltage Range.................................................................... 18 Functional Block Diagrams............................................................. 1 Power-On of the AD7834/AD7835.............................................. 19 Revision History ............................................................................... 2 Microprocessor Interfacing........................................................... 20 Specifications..................................................................................... 3 AD7834 to 80C51 Interface ...................................................... 20 AC Performance Characteristics ................................................ 5 AD7834 to 68HC11 Interface ................................................... 20 Timing Specifications .................................................................. 6 AD7834 to ADSP-2101 Interface ............................................. 20 Absolute Maximum Ratings............................................................ 7 AD7834 to DSP56000/DSP56001 Interface............................ 21 Thermal Resistance ...................................................................... 7 AD7834 to TMS32020/TMS320C25 Interface....................... 21 ESD Caution.................................................................................. 7 Interfacing the AD783516-Bit Interface.............................. 21 Pin Configurations and Function Descriptions ........................... 8 Interfacing the AD78358-Bit Interface................................ 22 Typical Performance Characteristics ........................................... 11 Applications Information .............................................................. 23 Terminology .................................................................................... 13 Serial Interface to Multiple AD7834s ...................................... 23 Theory of Operation ...................................................................... 14 Opto-Isolated Interface ............................................................. 23 DAC Architecture....................................................................... 14 Automated Test Equipment ...................................................... 23 Data LoadingAD7834 Serial Input Device ......................... 14 Power Supply Bypassing and Grounding................................ 24 Data LoadingAD7835 Parallel Loading Device ................. 14 Outline Dimensions....................................................................... 25 Unipolar Configuration............................................................. 15 Ordering Guide .......................................................................... 27 Bipolar Configuration................................................................ 16 Controlled Power-On of the Output Stage.................................. 17 REVISION HISTORY 8/07Rev. C to Rev. D Changes to Table 5 ........................................................................... 7 Added Table 6.................................................................................... 7 Changes to Table 8............................................................................ 9 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 27 7/05Rev. B to Rev. C Updated Format..................................................................Universal Changes to Figure 40...................................................................... 25 Changes to Ordering Guide .......................................................... 27 7/03Rev. A to Rev. B Revision 0: Initial Version Rev. D Page 2 of 28