Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9142 FEATURES GENERAL DESCRIPTION Very small inherent latency variation: <2 DAC clock cycles The AD9142 is a dual, 16-bit, high dynamic range digital-to- Proprietary low spurious and distortion design analog converter (DAC) that provides a sample rate of 1600 MSPS, 6-carrier GSM ACLR = 79 dBc at 200 MHz IF permitting a multicarrier generation up to the Nyquist frequency. SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF The AD9142 TxDAC+ includes features optimized for direct Flexible 16-bit LVDS interface conversion transmit applications, including complex digital mod- Supports word and byte load ulation, input signal power detection, and gain, phase, and offset Multiple chip synchronization compensation. The DAC outputs are optimized to interface Fixed latency and data generator latency compensation seamlessly with analog quadrature modulators, such as the Selectable 2, 4, 8 interpolation filter ADL537x F-MOD series and the ADRF670x series from Analog Low power architecture Devices, Inc. A 3-wire serial port interface provides for the pro- f /4 power saving coarse mixer S gramming/readback of many internal parameters. Full-scale Input signal power detection output current can be programmed over a range of 9 mA to 33 mA. Emergency stop for downstream analog circuitry The AD9142 is available in a 72-lead LFCSP. protection PRODUCT HIGHLIGHTS FIFO error detection 1. Advanced low spurious and distortion design techniques On-chip numeric control oscillator allows carrier placement provide high quality synthesis of wideband signals from anywhere in the DAC Nyquist bandwidth baseband to high intermediate frequencies. Transmit enable function for extra power saving 2. Very small inherent latency variation simplifies both software High performance, low noise PLL clock multiplier and hardware design in the system. It allows easy multichip Digital gain and phase adjustment for sideband suppression synchronization for most applications. Digital inverse sinc filter 3. New low power architecture improves power efficiency Supports single DAC mode Low power: 2.0 W at 1.6 GSPS, 1.7 W at 1.25 GSPS, full (mW/MHz/channel) by 30%. operating conditions 4. Input signal power and FIFO error detection simplify 72-lead LFCSP designs for downstream analog circuitry protection. 5. Programmable transmit enable function allows easy design APPLICATIONS balance between power consumption and wakeup time. Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2012 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AD9142 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Signal Power Detection and Protection ........................ 30 Applications ....................................................................................... 1 Transmit Enable Function ......................................................... 31 General Description ......................................................................... 1 Digital Function Configuration ............................................... 31 Product Highlights ........................................................................... 1 Multidevice Synchronization and Fixed Latency ....................... 32 Revision History ............................................................................... 3 Very Small Inherent Latency Variation ................................... 32 Functional Block Diagram .............................................................. 4 Further Reducing the Latency Variation ................................. 32 Specifications ..................................................................................... 5 Synchronization Implementation ............................................ 33 DC Specifications ......................................................................... 5 Synchronization Procedures ..................................................... 33 Digital Specifications ................................................................... 6 Interrupt Request Operation ........................................................ 34 DAC Latency Specifications ........................................................ 7 Interrupt Working Mechanism ................................................ 34 Latency Variation Specifications ................................................ 7 Interrupt Service Routine .......................................................... 34 AC Specifications .......................................................................... 7 Temperature Sensor ....................................................................... 35 Operating Speed Specifications .................................................. 8 DAC Input Clock Configurations ................................................ 36 Absolute Maximum Ratings ....................................................... 9 Driving the DACCLK and REFCLK Inputs ........................... 36 Thermal Resistance ...................................................................... 9 Direct Clocking .......................................................................... 36 ESD Caution .................................................................................. 9 Clock Multiplication .................................................................. 36 Pin Configuration and Function Descriptions ........................... 10 PLL Settings ................................................................................ 37 Typical Performance Characteristics ........................................... 12 Configuring the VCO Tuning Band ........................................ 37 Terminology .................................................................................... 17 Automatic VCO Band Select .................................................... 37 Serial Port Operation ..................................................................... 18 Manual VCO Band Select ......................................................... 37 Data Format ................................................................................ 18 Analog Outputs............................................................................... 38 Serial Port Pin Descriptions ...................................................... 18 Transmit DAC Operation .......................................................... 38 Serial Port Options ..................................................................... 18 Interfacing to Modulators ......................................................... 39 Data Interface .................................................................................. 20 Reducing LO Leakage and Unwanted Sidebands .................. 40 LVDS Input Data Ports .............................................................. 20 Example Start-Up Routine ............................................................ 41 Word Interface Mode ................................................................. 20 Device Configuration Register Map and Description ............... 42 Byte Interface Mode ................................................................... 20 SPI Configure Register .............................................................. 44 Data Interface Configuration Options .................................... 20 Power-Down Control Register ................................................. 44 Interface Delay Line ................................................................... 22 Interrupt Enable0 Register ........................................................ 44 FIFO Operation .............................................................................. 23 Interrupt Enable1 Register ........................................................ 44 Resetting the FIFO ..................................................................... 24 Interrupt Flag0 Register ............................................................. 45 Serial Port Initiated FIFO Reset ............................................... 24 Interrupt Flag1 Register ............................................................. 45 Frame Initiated FIFO Reset ....................................................... 24 Interrupt Select0 Register .......................................................... 45 Digital Datapath .............................................................................. 26 Interrupt Select1 Register .......................................................... 46 Interpolation Filters ................................................................... 26 DAC Clock Receiver Control Register .................................... 46 Digital Modulation ..................................................................... 28 Ref Clock Receiver Control Register ....................................... 46 Datapath Configuration ............................................................ 29 PLL Control Register ................................................................. 47 Digital Quadrature Gain and Phase Adjustment ................... 29 PLL Control Register ................................................................. 47 DC Offset Adjustment ............................................................... 29 PLL Control Register ................................................................. 47 Inverse Sinc Filter ....................................................................... 30 PLL Status Register ..................................................................... 48 Rev. 0 Page 2 of 64