14-Bit, 160 MSPS, 2/4/8 Interpolating Dual TxDAC+ Digital-to-Analog Converter AD9775 FEATURES Versatile input data interface Twos complement/straight binary data coding 14-bit resolution, 160 MSPS/400 MSPS input/output Dual-port or single-port interleaved input data data rate Single 3.3 V supply operation Selectable 2/4/8 interpolating filter Power dissipation: 1.2 W 3.3 V typical Programmable channel gain and offset adjustment On-chip, 1.2 V reference f /4, f /8 digital quadrature modulation capability S S 80-lead, thin quad flat package, exposed pad (TQFP EP) Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture APPLICATIONS Fully compatible SPI port Communications Excellent ac performance Analog quadrature modulation architecture SFDR: 71 dBc 2 MHz to 35 MHz 3G, multicarrier GSM, TDMA, CDMA systems W-CDMA ACPR: 71 dB IF = 19.2 MHz Broadband wireless, point-to-point microwave radios Internal PLL clock multiplier Instrumentation/ATE Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible FUNCTIONAL BLOCK DIAGRAM IDAC COS AD9775 HALF- HALF- HALF- GAIN OFFSET BAND BAND BAND DAC DAC FILTER1* FILTER2* FILTER3* DATA SIN ASSEMBLER IMAGE 14 16 16 16 16 REJECTION/ I I/Q DAC DUAL DAC LATCH f /2, 4, 8 DAC GAIN/OFFSET MODE REGISTERS I AND Q BYPASS NONINTERLEAVED MUX OR INTERLEAVED SIN DATA 16 16 16 16 Q LATCH 14 FILTER BYPASS COS WRITE MUX MUX CONTROL I SELECT IDAC OUT /2 (f ) DAC CLOCK OUT /2 /2 /2 SPI INTERFACE AND PRESCALER DIFFERENTIAL CONTROL REGISTERS CLK PHASE DETECTOR AND VCO * HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR ZERO STUFFING ONLY PLL CLOCK MULTIPLIER AND CLOCK DIVIDER Figure 1. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. VREF IOFFSET 02858-001AD9775 TABLE OF CONTENTS Features .............................................................................................. 1 1R/2R Mode ................................................................................ 25 Applications....................................................................................... 1 Clock Input Configurations...................................................... 25 Functional Block Diagram .............................................................. 1 Programmable PLL .................................................................... 26 Revision History ............................................................................... 3 Power Dissipation....................................................................... 27 General Description ......................................................................... 4 Sleep/Power-Down Modes........................................................ 28 Product Highlights ....................................................................... 4 Two-Port Data Input Mode ...................................................... 28 Specifications..................................................................................... 5 PLL Enabled, Two-Port Mode .................................................. 28 DC Specifications ......................................................................... 5 DATACLK Inversion.................................................................. 29 Dynamic Specifications ............................................................... 6 DATACLK Driver Strength....................................................... 29 Digital Specifications ................................................................... 7 PLL Enabled, One-Port Mode .................................................. 29 Digital Filter Specifications ......................................................... 8 ONEPORTCLK Inversion......................................................... 29 Absolute Maximum Ratings............................................................ 9 ONEPORTCLK Driver Strength.............................................. 30 ESD Caution.................................................................................. 9 IQ Pairing .................................................................................... 30 Thermal Resistance ...................................................................... 9 PLL Disabled, Two-Port Mode................................................. 30 Pin Configuration and Function Descriptions........................... 10 PLL Disabled, One-Port Mode................................................. 30 Typical Performance Characteristics ........................................... 12 Digital Filter Modes ................................................................... 31 Terminology .................................................................................... 17 Amplitude Modulation.............................................................. 31 Mode Control (via SPI Port) ......................................................... 18 Modulation, No Interpolation .................................................. 32 Register Descriptions ..................................................................... 19 Modulation, Interpolation = 2 ............................................... 33 Address 0x00 ............................................................................... 19 Modulation, Interpolation = 4 ............................................... 34 Address 0x01 ............................................................................... 19 Modulation, Interpolation = 8 ............................................... 35 Address 0x02 ............................................................................... 19 Zero Stuffing ............................................................................... 36 Address 0x03 ............................................................................... 20 Interpolating (Complex Mix Mode)........................................ 36 Address 0x04 ............................................................................... 20 Operations on Complex Signals............................................... 36 Address 0x05, Address 0x09 ..................................................... 20 Complex Modulation and Image Rejection of Baseband Signals .......................................................................................... 37 Address 0x06, Address 0x0A..................................................... 20 Image Rejection and Sideband Suppression of Modulated Address 0x07, Address 0x0B ..................................................... 20 Carriers ........................................................................................ 38 Address 0x08, Address 0x0C..................................................... 20 Applying the Output Configurations........................................... 42 Address 0x08, Address 0x0C..................................................... 20 Unbuffered Differential Output, Equivalent Circuit ............. 42 Functional Description .................................................................. 21 Differential Coupling Using a Transformer............................ 42 Serial Interface for Register Control ........................................ 21 Differential Coupling Using an Op Amp................................ 43 General Operation of the Serial Interface ............................... 21 Interfacing the AD9775 with the AD8345 Quadrature Instruction Byte .......................................................................... 22 Modulator.................................................................................... 43 Serial Interface Port Pin Descriptions ..................................... 22 Evaluation Board ............................................................................ 44 MSB/LSB Transfers..................................................................... 22 Outline Dimensions....................................................................... 54 Notes on Serial Port Operation ................................................ 22 Ordering Guide .......................................................................... 54 DAC Operation........................................................................... 24 Rev. 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