16-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+ D/A Converter AD9777 Versatile input data interface FEATURES Twos complement/straight binary data coding 16-bit resolution, 160 MSPS/400 MSPS input/output Dual-port or single-port interleaved input data data rate Single 3.3 V supply operation Selectable 2/4/8 interpolating filter Power dissipation: typical 1.2 W 3.3 V Programmable channel gain and offset adjustment On-chip 1.2 V reference fS/4, fS/8 digital quadrature modulation capability 80-lead thin quad flat package, exposed pad (TQFP EP) Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture APPLICATIONS Fully compatible SPI port Communications Excellent ac performance Analog quadrature modulation architecture SFDR 73 dBc 2 MHz to 35 MHz 3G, multicarrier GSM, TDMA, CDMA systems WCDMA ACPR 71 dB IF = 19.2 MHz Broadband wireless, point-to-point microwave radios Internal PLL clock multiplier Instrumentation/ATE Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatible FUNCTIONAL BLOCK DIAGRAM IDAC COS AD9777 HALF- HALF- HALF- GAIN OFFSET BAND BAND BAND DAC DAC FILTER1* FILTER2* FILTER3* DATA SIN ASSEMBLER IMAGE 16 16 16 16 16 REJECTION/ I I/Q DAC DUAL DAC LATCH f /2, 4, 8 GAIN/OFFSET DAC MODE REGISTERS I AND Q BYPASS NONINTERLEAVED MUX OR INTERLEAVED SIN 16 DATA 16 16 16 Q LATCH 16 FILTER COS BYPASS WRITE MUX MUX CONTROL IDAC I SELECT OUT /2 (f ) DAC CLOCK OUT /2 /2 /2 SPI INTERFACE AND PRESCALER DIFFERENTIAL CONTROL REGISTERS CLK PHASE DETECTOR AND VCO * HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR ZERO STUFFING ONLY PLL CLOCK MULTIPLIER AND CLOCK DIVIDER Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. VREF IOFFSET 02706-001AD9777 TABLE OF CONTENTS Features .............................................................................................. 1 Sleep/Power-Down Modes........................................................ 29 Applications....................................................................................... 1 Two Port Data Input Mode ....................................................... 29 General Description ......................................................................... 4 PLL Enabled, Two-Port Mode .................................................. 30 Product Highlights ....................................................................... 4 DATACLK Inversion.................................................................. 30 Specifications..................................................................................... 5 DATACLK Driver Strength....................................................... 30 DC Specifications ......................................................................... 5 PLL Enabled, One-Port Mode .................................................. 30 Dynamic Specifications ............................................................... 6 ONEPORTCLK Inversion......................................................... 31 Digital Specifications ................................................................... 7 ONEPORTCLK Driver Strength.............................................. 31 Digital Filter Specifications ......................................................... 8 IQ Pairing .................................................................................... 31 Absolute Maximum Ratings............................................................ 9 PLL Disabled, Two-Port Mode................................................. 31 Thermal Characteristics .............................................................. 9 PLL Disabled, One-Port Mode................................................. 32 ESD Caution.................................................................................. 9 Digital Filter Modes ................................................................... 32 Pin Configuration and Function Descriptions........................... 10 Amplitude Modulation.............................................................. 32 Terminology .................................................................................... 12 Modulation, No Interpolation .................................................. 34 Typical Performance Characteristics ........................................... 13 Modulation, Interpolation = 2 ............................................... 35 Mode Control (via SPI Port)..................................................... 18 Modulation, Intermodulation = 4 ......................................... 36 Register Description................................................................... 20 Modulation, Intermodulation = 8 ......................................... 37 Functional Description .................................................................. 22 Zero Stuffing ............................................................................... 38 Serial Interface for Register Control ........................................ 22 Interpolating (Complex Mix Mode)........................................ 38 General Operation of the Serial Interface ............................... 22 Operations on Complex Signals............................................... 38 Instruction Byte .......................................................................... 23 Complex Modulation and Image Rejection of Baseband Signals .......................................................................................... 39 R/W .............................................................................................. 23 Image Rejection and Sideband Suppressions of Modulated N1, N0.......................................................................................... 23 Carriers ........................................................................................ 41 A4, A3, A2, A1, A0..................................................................... 23 Applying the Output Configurations........................................... 46 Serial Interface Port Pin Descriptions ..................................... 23 Unbuffered Differential Output, Equivalent Circuit ............. 46 MSB/LSB Transfers..................................................................... 23 Differential Coupling Using a Transformer............................ 46 Notes on Serial Port Operation ................................................ 25 Differential Coupling Using an Op Amp................................ 47 DAC Operation........................................................................... 25 Interfacing with the AD8345 Quadrature Modulator........... 47 1R/2R Mode ................................................................................ 26 Evaluation Board ............................................................................ 48 CLOCK Input Configuration ................................................... 26 Outline Dimensions ....................................................................... 58 Programmable PLL .................................................................... 27 Ordering Guide .......................................................................... 58 Power Dissipation....................................................................... 29 Rev. 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