1 GSPS Direct Digital Synthesizer AD9858 FEATURES GENERAL DESCRIPTION 1 GSPS internal clock speed The AD9858 is a direct digital synthesizer (DDS) featuring a Up to 2 GHz input clock (selectable divide-by-2) 10-bit digital-to-analog converter (DAC) operating up to 1 GSPS. Integrated 10-bit DAC The AD9858 uses advanced DDS technology coupled with an Excellent phase noise and SFDR internal high speed, high performance DAC to form a digitally 32-bit programmable frequency register programmable, complete high frequency synthesizer capable of Simplified 8-bit parallel and SPI serial control interface generating a frequency-agile analog output sine wave at up to Automatic frequency sweeping capability 400 MHz. The AD9858 is designed to provide fast frequency 4 frequency profiles hopping and fine tuning resolution (32-bit frequency tuning 3.3 V power supply word). The frequency tuning and control words are loaded into Power dissipation: 2 W typical the AD9858 via parallel (8-bit) or serial loading formats. The Integrated programmable charge pump and phase AD9858 contains an integrated charge pump (CP) and phase frequency detector with fast lock circuit frequency detector (PFD) for synthesis applications requiring Isolated charge pump supply up to 5 V the combination of a high speed DDS along with phase-locked Integrated 2 GHz mixer loop (PLL) functions. An analog mixer is also provided on chip for applications requiring the combination of a DDS, PLL, and APPLICATIONS mixer, such as frequency translation loops and tuners. The AD9858 VHF/UHF LO synthesis also features a divide-by-2 on the clock input, allowing the external Tuners reference clock to be as high as 2 GHz. Instrumentation The AD9858 is specified to operate over the extended industrial Agile clock synthesis temperature range of 40C to +85C. Cellular base station hopping synthesizers Radars SONET/SDH clock synthesis FUNCTIONAL BLOCK DIAGRAM LO LO IF IF RF RF DIV M DIV PHASE DETECTOR PD N AD9858 CHARGE ANALOG CP PUMP MULTIPLIER DIGITAL PLL CPISET FREQUENCY ACCUMULATOR PHASE ACCUMULATOR DACISET PHASE-TO- IOUT 32 15 15 10 AMPLITUDE DAC CONVERSION IOUT 14 SYSCLK 32 32 TIMING AND CONTROL LOGIC RESET FUD SYNCLK 8 CONTROL REGISTERS M REFCLK POWER- U DOWN REFCLK 2 X LOGIC PS0 PS1 I/O PORT (SER/PAR) Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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DELTA FREQUENCY WORD DELTA FREQUENCY RAMP RATE FREQUENCY ACCUMULATOR RESET FREQUENCY TUNING WORD PHASE SYNC ACCUMULATOR RESET PHASE OFFSET ADJUST 03166-001AD9858 TABLE OF CONTENTS Features .............................................................................................. 1 Component Blocks ..................................................................... 14 Applications ....................................................................................... 1 Modes of Operation ................................................................... 16 General Description ......................................................................... 1 Synchronization .......................................................................... 18 Functional Block Diagram .............................................................. 1 Programming the AD9858 ........................................................ 19 Revision History ............................................................................... 2 Register Map ................................................................................... 22 Electrical Specifications ................................................................... 3 Register Bit Descriptions ........................................................... 23 Absolute Maximum Ratings ............................................................ 6 Other Registers ........................................................................... 25 Thermal Performance .................................................................. 6 User Profile Registers ................................................................. 25 Explanation of Test Levels ........................................................... 6 Applications Information .............................................................. 27 ESD Caution .................................................................................. 6 Evaluation Boards ...................................................................... 28 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 29 Typical Performance Characteristics ............................................. 9 Warning ....................................................................................... 29 Theory of Operation ...................................................................... 14 Ordering Guide .......................................................................... 29 REVISION HISTORY 2/09Rev. B to Rev. C Changes to Delta Frequency Tuning Word (DFTW) Section, Changes to Features Section, General Description Section, and Delta Frequency Ramp Rate Word (DFRRW) Section, and Figure 1 .............................................................................................. 1 Phase Offset Control Section ........................................................ 25 Changes to Table 1 ............................................................................ 3 Changes to Profile Selection Section ........................................... 26 Deleted Frequency Tuning Control Section ............................... 27 Changes to Table 2 ............................................................................ 6 Added Thermal Performance Section ........................................... 6 Changed AD9858 Application Suggestions Section to Changes to Figure 3, Figure 4, and Figure 5.................................. 9 Applications Information Section ................................................ 27 Changes to Figure 9, Figure 10 Caption, Figure 11 Caption, Changes to Table 13 ....................................................................... 28 Figure 13, and Figure 14 ................................................................ 10 Added Exposed Paddle Notation to Outline Dimensions ........ 29 Changes to Figure 17 ...................................................................... 11 Changes to Theory of Operation Section and DAC Output 4/07Rev. A to Rev. B Section .............................................................................................. 14 Changed EPAD to TQFP EP ............................................ Universal Updated Outline Dimensions ....................................................... 31 Changes to Charge Pump Section ................................................ 15 Changes to Modes of Operation Section ..................................... 16 Changes to Single-Tone Mode Section and Frequency Sweeping 11/03Rev. 0 to Rev. A Mode Section................................................................................... 17 Changes to Specifications ................................................................. 5 Changes to SYNCLK and FUD Pins Section and Figure 33 ..... 18 Moved ESD Caution to ..................................................................... 6 Changes to I/O Port Functionality Section, Parallel Moved Pin Configuration to ............................................................ 7 Programming Mode Section, and Figure 35 ............................... 20 Moved Pin Function Description to ............................................... 8 Changes to Figure 36 and Serial Programming Changes to Equations .................................................................... 19 Changes to Delta Frequency Ramp Rate Word (DFRRW) ....... 27 Mode Section................................................................................... 21 Changes to Table 6 .......................................................................... 22 Changes to Control Function Register (CFR) Section .............. 23 4/03Revision 0: Initial Version Changes to CFR 21 : Load Delta Frequency Timer Section .... 24 Changed CFR 14 : Sine/Cosine Select Bit Section to CFR 14 : Enable Sine Output Bit Section ..................................................... 24 Rev. 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