Product Information


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Display Interface IC Graphics IF Chip w/3 8-bit ADC

Manufacturer: Analog Devices
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges

Price (USD)

1: USD 16.6437 ea
Line Total: USD 16.6437

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock

Ships to you between Thu. 08 Jun to Mon. 12 Jun

MOQ : 1
Multiples : 1

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Analog Devices

1 : USD 16.6437
10 : USD 14.994
25 : USD 14.5278
90 : USD 12.5273
270 : USD 12.0306
540 : USD 11.4369
1080 : USD 11.1704

Analog Devices
Product Category
Display Interface IC
Mounting Style
Package / Case
Operating Supply Voltage
3.3 V
Minimum Operating Temperature
- 40 C
Maximum Operating Temperature
+ 85 C
Analog Devices
Factory Pack Quantity :
Hts Code
Product Type
Display Interface Ic
Interface Ics
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110 MSPS/140 MSPS Analog Interface a for Flat Panel Displays AD9883A FEATURES FUNCTIONAL BLOCK DIAGRAM Industrial Temperature Range Operation 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 8 R CLAMP A/D R AIN OUTA 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 8 3.3 V Power Supply G CLAMP A/D AIN G OUTA Full Sync Processing Sync Detect for Hot Plugging 8 Midscale Clamping B CLAMP A/D B AIN OUTA Power-Down Mode MIDSCV Low Power: 500 mW Typical HSYNC DTACK 4:2:2 Output Format Mode SYNC COAST PROCESSING HSOUT AND CLOCK APPLICATIONS CLAMP VSOUT GENERATION RGB Graphics Processing FILT SOGOUT LCD Monitors and Projectors REF REF Plasma Display Panels BYPASS SCL SERIAL REGISTER Scan Converters SDA AND AD9883A POWER MANAGEMENT Microdisplays A 0 Digital TV GENERAL DESCRIPTION 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. The AD9883A is a complete 8-bit, 140 MSPS, monolithic analog When the COAST signal is presented, the PLL maintains its interface optimized for capturing RGB graphics signals from output frequency in the absence of Hsync. A sampling phase personal computers and workstations. Its 140 MSPS encode adjustment is provided. Data, Hsync, and clock output phase rate capability and full power analog bandwidth of 300 MHz relationships are maintained. The AD9883A also offers full sync supports resolutions up to SXGA (1280 1024 at 75 Hz). processing for composite sync and sync-on-green applications. The AD9883A includes a 140 MHz triple ADC with internal A clamp signal is generated internally or may be provided by 1.25 V reference, a PLL, and programmable gain, offset, and the user through the CLAMP input pin. This interface is fully clamp control. The user provides only a 3.3 V power supply, programmable via a 2-wire serial interface. analog input, and Hsync and COAST signals. Three-state Fabricated in an advanced CMOS process, the AD9883A is pro- CMOS outputs may be powered from 2.5 V to 3.3 V. vided in a space-saving 80-lead LQFP surface-mount plastic package The AD9883As on-chip PLL generates a pixel clock from the and is specified over the 40C to +85C temperature range. Hsync input. Pixel clock output frequencies range from 12 MHz to REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved.AD9883ASPECIFICATIONS Analog Interface (V = 3.3 V, V = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.) D DD Test AD9883AKST-110 AD9883AKST-140 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity 25CI 0.5 +1.25/1.0 0.5 +1.35/1.0 LSB Full VI +1.35/1.0 +1.45/1.0 LSB Integral Nonlinearity 25CI 0.5 1.85 0.5 2.0 LSB Full VI 2.0 2.3 LSB No Missing Codes Full VI Guaranteed Guaranteed ANALOG INPUT Input Voltage Range Minimum Full VI 0.5 0.5 V p-p Maximum Full VI 1.0 1.0 V p-p Gain Tempco 25CV 100 100 ppm/C Input Bias Current 25CIV 1 1 A Full IV 1 1 A Input Offset Voltage Full VI 7 50 7 70 mV Input Full-Scale Matching Full VI 1.5 6.0 1.5 8.0 % FS Offset Adjustment Range Full VI 46 49 52 46 49 52 % FS REFERENCE OUTPUT Output Voltage Full VI 1.20 1.25 1.32 1.20 1.25 1.32 V Temperature Coefficient Full V 50 50 ppm/C SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 110 140 MSPS Minimum Conversion Rate Full IV 10 10 MSPS Data to Clock Skew Full IV 0.5 +2.0 0.5 +2.0 ns t Full VI 4.7 4.7 s BUFF t Full VI 4.0 4.0 s STAH t Full VI 0 0 s DHO t Full VI 4.7 4.7 s DAL t Full VI 4.0 4.0 s DAH t Full VI 250 250 ns DSU t Full VI 4.7 4.7 s STASU t Full VI 4.0 4.0 s STOSU HSYNC Input Frequency Full IV 15 110 15 110 kHz Maximum PLL Clock Rate Full VI 110 140 MHz Minimum PLL Clock Rate Full IV 12 12 MHz 1 1 PLL Jitter 25CIV 400 700 400 700 ps p-p 1 1 Full IV 1000 1000 ps p-p Sampling Phase Tempco Full IV 15 15 ps/C DIGITAL INPUTS Input Voltage, High (V ) Full VI 2.5 2.5 V IH Input Voltage, Low (V ) Full VI 0.8 0.8 V IL Input Voltage, High (V ) Full V 1.0 1.0 A IH Input Voltage, Low (V ) Full V +1.0 +1.0 A IL Input Capacitance 25CV 3 3 pF 2 REV. B

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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