CCD Signal Processor with V-Driver and Precision Timing Generator AD9923A FEATURES GENERAL DESCRIPTION Integrated 15-channel V-driver The AD9923A is a complete 36 MHz front-end solution for 12-bit, 36 MHz analog-to-digital converter (ADC) digital still cameras and other CCD imaging applications. Similar register map to the AD9923 Similar to the AD9923 product, the AD9923A includes the 5-field, 10-phase vertical clock support analog front end (AFE), a fully programmable timing generator Complete on-chip timing generator (TG), and a 15-channel vertical driver (V-driver). A Precision Precision Timing core with <600 ps resolution Timingcore allows adjustment of high speed clocks with Correlated double sampler (CDS) approximately 600 ps resolution at 36 MHz operation. 6 dB to 42 dB 10-bit variable gain amplifier (VGA) The on-chip V-driver supports up to 15 channels for use with Black level clamp with variable level control 5-field, 10-phase CCDs. On-chip 3 V horizontal and RG drivers 2-phase and 4-phase H-clock modes The analog front end includes black level clamping, CDS, VGA, Electronic and mechanical shutter support and a 12-bit ADC. The timing generator and V-driver provide On-chip driver for external crystal all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor On-chip sync generator with external sync input gate pulses, substrate clock, and substrate bias control. The 8 mm 8 mm CSP BGA package with 0.65 mm pitch internal registers are programmed using a 3-wire serial interface. APPLICATIONS Digital still cameras Packaged in an 8 mm 8 mm CSP BGA, the AD9923A is specified over an operating temperature range of 25C to +85C. FUNCTIONAL BLOCK DIAGRAM REFT REFB 3dB, 0dB, +3dB, +6dB +6dB TO +42dB AD9923A VREF 12 12-BIT D0 TO D11 CCDIN CDS VGA ADC CLAMP RG DCLK INTERNAL CLOCKS HL HORIZONTAL DRIVERS 4 H1 TO H4 PRECISION TIMING SL GENERATOR 13 INTERNAL SDI REGISTERS XV1 TO SCK XV13 V1, V2, V3, VERTICAL 15 V4, V5A, V5B, V-DRIVER 8 TIMING SYNC V6, V7A, V7B, CONTROL GENERATOR XSG1 TO V8, V9, V10, XSG8 V11, V12, V13 2 XSUBCK, 3 XSUBCNT SUBCK VSUB, MSHUT, HD VD SYNC CLI CLO STROBE Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20062010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05586-001AD9923A TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 14 Applications ....................................................................................... 1 Precision Timing High Speed Timing Generation ................. 15 General Description ......................................................................... 1 Horizontal Clamping and Blanking ......................................... 18 Functional Block Diagram .............................................................. 1 Vertical Timing Generation ...................................................... 24 Revision History ............................................................................... 2 Vertical Timing Example ........................................................... 38 Specif icat ions ..................................................................................... 3 Vertical Driver Signal Configuration ........................................... 40 Digital Specifications ................................................................... 4 Shutter Timing Control ............................................................. 44 H-Driver Specifications ............................................................... 4 Example of Exposure and Readout of Interlaced Frame....... 53 Vertical Driver Specifications ..................................................... 4 FG TRIG Operation .................................................................. 54 Analog Specifications ................................................................... 5 Analog Front End Description/Operation ............................. 55 Timing Specifications .................................................................. 6 Standby Mode Operation .......................................................... 60 Absolute Maximum Ratings ............................................................ 8 Circuit Layout Information ....................................................... 62 Thermal Resistance ...................................................................... 8 Serial Interface Timing .............................................................. 65 ESD Caution .................................................................................. 8 Layout of Internal Registers ...................................................... 66 Pin Configuration and Function Descriptions ............................. 9 Updating New Register Values ................................................. 67 Typical Performance Characteristics ........................................... 11 Complete Register Listing ......................................................... 68 Equivalent Circuits ......................................................................... 12 Outline Dimensions ....................................................................... 84 Terminology .................................................................................... 13 Ordering Guide .......................................................................... 84 REVISION HISTORY 1/10Rev. 0 to Rev. A Changes to Table 6 ............................................................................ 6 Added Table 8 Renumbered Sequentially .................................... 8 Changes to Individual HBLK Patterns Section .......................... 20 Changes to Table 13 ........................................................................ 20 Change to SUBCK: High Precision Operation Section ............. 45 Changes to Manual Control Section ............................................ 49 10/06Revision 0: Initial Version Rev. A Page 2 of 84