AD9957PCBZ

1 GSPS Quadrature Digital Upconverter with 18-Bit I/Q Data Path and 14-Bit DAC Data Sheet AD9957 FEATURES GENERAL DESCRIPTION 1 GSPS internal clock speed (up to 400 MHz analog output) The AD9957 functions as a universal I/Q modulator and agile Integrated 1 GSPS 14-bit DAC upconverter for communications systems where cost, size, power 250 MSPS input data rate consumption, and dynamic performance are critical. The Phase noise 125 dBc/Hz (400 MHz carrier at 1 kHz offset) AD9957 integrates a high speed, direct digital synthesizer Excellent dynamic performance >80 dB narrow-band SFDR (DDS), a high performance, high speed, 14-bit digital-to-analog 8 programmable profiles for shift keying converter (DAC), clock multiplier circuitry, digital filters, and Sin(x)/(x) correction (inverse sinc filter) other DSP functions onto a single chip. It provides baseband Reference clock multiplier upconversion for data transmission in a wired or wireless Internal oscillator for a single crystal operation communications system. Software and hardware controlled power-down Integrated RAM The AD9957 is the third offering in a family of quadrature Phase modulation capability digital upconverters (QDUCs) that includes the AD9857 and Multichip synchronization AD9856. It offers performance gains in operating speed, power Easy interface to Blackfin SPORT consumption, and spectral performance. Unlike its predecessors, Interpolation factors from 4 to 252 it supports a 16-bit serial input mode for I/Q baseband data. Interpolation DAC mode The device can alternatively be programmed to operate either as Gain control DAC a single tone, sinusoidal source or as an interpolating DAC. Internal divider allows references up to 2 GHz The reference clock input circuitry includes a crystal oscillator, 1.8 V and 3.3 V power supplies a high speed, divide-by-two input, and a low noise PLL for 100-lead TQFP EP package multiplication of the reference clock frequency. APPLICATIONS The user interface to the control functions includes a serial port HFC data, telephony, and video modems easily configured to interface to the SPORT of the Blackfin Wireless base station transmissions DSP and profile pins to enable fast and easy shift keying of any Broadband communications transmissions signal parameter (phase, frequency, or amplitude). Internet telephony FUNCTIONAL BLOCK DIAGRAM I DATA FORMAT AND FOR 14-BIT DAC I/Q DATA INTERPOLATE XMIT Q NCO AD9957 TIMING AND REFERENCE CLOCK CONTROL INPUT CIRCUITRY USER INTERFACE REFERENCE CLOCK INPUT Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 06384-001AD9957 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RAM Control .................................................................................. 27 Applications ....................................................................................... 1 RAM Overview ........................................................................... 27 General Description ......................................................................... 1 RAM Segment Registers ............................................................ 27 Functional Block Diagram .............................................................. 1 RAM State Machine ................................................................... 27 Revision History ............................................................................... 4 RAM Trigger (RT) Pin ............................................................... 27 Specifications ..................................................................................... 5 Load/Retrieve RAM Operation ................................................ 28 Electrical Specifications ............................................................... 5 RAM Playback Operation ......................................................... 28 Absolute Maximum Ratings ............................................................ 8 Overview of RAM Playback Modes ......................................... 29 ESD Caution .................................................................................. 8 RAM Ramp-Up Mode ........................................................... 29 Pin Configuration and Function Descriptions ............................. 9 RAM Bidirectional Ramp Mode .......................................... 30 Typical Performance Characteristics ........................................... 12 RAM Continuous Bidirectional Ramp Mode .................... 32 Modes of Operation ....................................................................... 16 RAM Continuous Recirculate Mode ................................... 33 Overview ...................................................................................... 16 Clock Input (REF CLK) ................................................................ 34 Quadrature Modulation Mode ................................................. 17 REFCLK Overview ..................................................................... 34 BlackFin Interface (BFI) Mode ................................................. 18 Crystal Driven REF CLK ......................................................... 34 Interpolating DAC Mode .......................................................... 19 Direct Driven REF CLK ........................................................... 34 Single Tone Mode ....................................................................... 20 Phase-Locked Loop (PLL) Multiplier ...................................... 35 Signal Processing ............................................................................ 21 PLL Charge Pump ...................................................................... 36 Parallel Data Clock (PDCLK) ................................................... 21 External PLL Loop Filter Components ................................... 36 Transmit Enable Pin (TxENABLE) .......................................... 21 PLL Lock Indication .................................................................. 36 Input Data Assembler ................................................................ 22 Additional Features ........................................................................ 37 Inverse CCI Filter ....................................................................... 23 Output Shift Keying (OSK) ....................................................... 37 Fixed Interpolator (4) .............................................................. 23 Manual OSK ............................................................................ 37 Programmable Interpolating Filter .......................................... 24 Automatic OSK ....................................................................... 37 QDUC Mode ........................................................................... 24 Profiles ......................................................................................... 38 BFI Mode ................................................................................. 24 I/O UPDATE Pin ...................................................................... 38 Quadrature Modulator .............................................................. 25 Automatic I/O Update ............................................................... 38 DDS Core ..................................................................................... 25 Power-Down Control ................................................................ 39 Inverse Sinc Filter ....................................................................... 25 General-Purpose I/O (GPIO) Port .......................................... 39 Output Scale Factor (OSF) ........................................................ 26 Synchronization of Multiple Devices ........................................... 40 14-Bit DAC .................................................................................. 26 Overview ..................................................................................... 40 Auxiliary DAC ........................................................................ 26 Clock Generator ......................................................................... 40 Rev. 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