36 V, 18 MHz, Low Noise, Fast Settling Single Supply, RRO, JFET Op Amp Data Sheet ADA4625-1 FEATURES PIN CONFIGURATION Wide gain bandwidth product: 18 MHz typical ADA4625-1 NC 1 8 NC High slew rate: 48 V/s typical IN 2 7 V+ Low voltage noise density: 3.3 nV/Hz typical at 1 kHz +IN 3 6 OUT Low peak-to-peak noise: 0.15 V p-p, 0.1 Hz to 10 Hz TOP VIEW Low input bias current: 15 pA typical at T = 25C (Not to Scale) A V 4 5 NC Low offset voltage: 80 V maximum at T = 25C A NOTES 1. NC = NO CONNECTION. DO NOT CONNECT TO THIS PIN. Offset voltage drift: 1.2 V/C maximum at T = 40C to 85C A 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND, Fast settling: 0.01% in 700 ns typical V+ OR V PLANE, OR LEAVE IT FLOATING. Wide range of operating voltages Figure 1. Dual-supply operation: 2.5 V to 18 V Single-supply operation: 5 V to 36 V The ADA4625-1 is unity-gain stable, and there is no phase Input voltage range includes V reversal when input range exceeds either supply rail by 200 mV. Rail-to-rail output The output is capable of driving loads up to 1000 pF and/or High capacitive load drive capability 600 loads. Output short-circuit current: 46 mA No phase reversal The ADA4625-1 is specified for operation over the extended Unity-gain stable industrial temperature range of 40C to +125C and operates from +5 V to +36 V (2.5 V to 18 V) with specifications at +5 V APPLICATIONS and 18 V. The ADA4625-1 is available in 8-lead SOIC package PLL filter amplifiers with an exposed pad (EPAD). Transimpedance amplifiers 100 Photodiode sensor interfaces V = 5V SY V = 18V SY Low noise charge amplifiers GENERAL DESCRIPTION The ADA4625-1 builds upon Analog Devices, Inc., industry leading high voltage, single-supply, rail-to-rail output (RRO), 10 precision junction field effect transistor (JFET) input op amps, taking that product type to a level of speed and low noise that has not been made available to the market previously. The ADA4625-1 provides optimal performance in high voltage, high gain, and low noise applications. The input common-mode voltage range includes the negative supply, and the output 1 1 10 100 1k 10k 100k swings rail to rail. This enables the user to maximize dynamic FREQUENCY (Hz) input range in low voltage, single supply applications without Figure 2. Voltage Noise Density vs. Frequency the need for a separate negative voltage power supply for ground sense. Table 1. Related Precision JFET Operational Amplifiers Single Dual Quad The combination of wide bandwidth, low noise, and low input Not applicable AD823A Not applicable bias current makes the ADA4625-1 especially suitable for AD8510 AD8512 AD8513 phase-locked loop (PLL), active filter amplifiers and for high AD8610 AD8620 Not applicable tuning voltage (VTUNE), voltage controlled oscillators (VCOs) ADA4610-1 ADA4610-2 ADA4610-4 and preamplifiers where low level signals require an amplifier ADA4622-1 ADA4622-2 ADA4622-4 that provides both high amplification and wide bandwidth. ADA4627-1/ADA4637-1 Not applicable Not applicable Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. VOLTAGE NOISE DENSITY (nV/ Hz) 15893-001 15893-157ADA4625-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Stage ................................................................................ 20 Applications ....................................................................................... 1 No Phase Inversion .................................................................... 21 General Description ......................................................................... 1 Supply Current ............................................................................ 21 Pin Configuration ............................................................................. 1 Applications Information .............................................................. 22 Revision History ............................................................................... 2 Active Loop Filter for Phase-Locked Loops (PLLs) .............. 22 Specif icat ions ..................................................................................... 3 ADA4625-1 Advantages and Design Example ....................... 23 Electrical Characteristics18 V Operation ........................... 3 Transimpedance Amplifier ....................................................... 24 Electrical Characteristics5 V Operation................................ 5 Recommended Power Solution ................................................ 28 Absolute Maximum Ratings ............................................................ 7 Input Overvoltage Protection ................................................... 28 Thermal Resistance ...................................................................... 7 Driving Capacitive Loads .......................................................... 28 ESD Caution .................................................................................. 7 Thermal Management ............................................................... 29 Pin Configuration and Function Descriptions ............................. 8 Outline Dimensions ....................................................................... 30 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 30 Theory of Operation ...................................................................... 20 Input and Gain Stages ................................................................ 20 REVISION HISTORY 10/2017Revision 0: Initial Version Rev. 0 Page 2 of 30