Dual Ultrafast Voltage Comparator ADCMP565 FEATURES FUNCTIONAL BLOCK DIAGRAM 300 ps propagation delay input to output 50 ps propagation delay dispersion NONINVERTING Q OUTPUT Differential ECL compatible outputs INPUT ADCMP565 Differential latch control INVERTING Q OUTPUT INPUT Robust input protection Input common-mode range 2.0 V to +3.0 V LATCH ENABLE LATCH ENABLE INPUT INPUT Input differential range 5 V 02820-0-001 Power supply sensitivity greater than 65 dB Figure 1. 200 ps minimum pulsewidth 5 GHz equivalent input rise time bandwidth GENERAL DESCRIPTION Typical output rise/fall of 160 ps SPT 9689 replacement The ADCMP565 is an ultrafast voltage comparator fabricated on Analog Devices proprietary XFCB process. The device APPLICATIONS features 300 ps propagation delay with less than 50 ps overdrive High speed instrumentation dispersion. Overdrive dispersion, a particularly important Scope and logic analyzer front ends characteristic of high speed comparators, is a measure of the Window comparators difference in propagation delay under differing overdrive High speed line receivers and signal restoration conditions. Threshold detection A fast, high precision differential input stage permits consis- Peak detection tent propagation delay with a wide variety of signals in the High speed triggers common-mode range from 2.0 V to +3.0 V. Outputs are Patient diagnostics complementary digital signals fully compatible with ECL 10 K Disk drive read channel detection and 10 KH logic families. The outputs provide sufficient drive Hand-held test instruments current to directly drive transmission lines terminated in 50 Zero-crossing detectors to 2 V. A latch input is included, which permits tracking, Clock drivers track-and-hold, or sample-and-hold modes of operation. Automatic test equipment The ADCMP565 is available in a 20-lead PLCC package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 2003 Analog Devices, Inc. All rights reserved. ADCMP565 TABLE OF CONTENTS Specifications..................................................................................... 3 Optimizing High Speed Performance ........................................9 Absolute Maximum Ratings............................................................ 5 Comparator Propagation Delay Dispersion ..............................9 Thermal Considerations.............................................................. 5 Comparator Hysteresis .............................................................. 10 ESD Caution.................................................................................. 5 Minimum Input Slew Rate Requirement................................ 10 Pin Configuration and Function Descriptions............................. 6 Typical Application Circuits ..................................................... 11 Timing Information ......................................................................... 8 Typical Performance Characteristics ........................................... 12 Application Information.................................................................. 9 Outline Dimensions ....................................................................... 14 Clock Timing Recovery............................................................... 9 Ordering Guide .......................................................................... 14 REVISION HISTORY Revision 0: Initial Version Rev. 0 Page 2 of 16