Integrated Synthesizer and VCO Data Sheet ADF4360-5 FEATURES GENERAL DESCRIPTION Output frequency range: 1200 MHz to 1400 MHz The ADF4360-5 is a fully integrated integer-N synthesizer Divide-by-2 output and voltage-controlled oscillator (VCO). The ADF4360-5 is 3.0 V to 3.6 V power supply designed for a center frequency of 1300 MHz. In addition, a 1.8 V logic compatibility divide-by-2 option is available, whereby the user gets an RF Integer-N synthesizer output of between 600 MHz and 700 MHz. Programmable dual-modulus prescaler 8/9, 16/17, 32/33 Programmable output power level Control of all the on-chip registers is through a simple 3-wire 3-wire serial interface interface. The device operates with a power supply ranging Analog and digital lock detect from 3.0 V to 3.6 V and can be powered down when not in use. Hardware and software power-down mode APPLICATIONS Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AV DV CE R DD DD SET ADF4360-5 MUXOUT MULTIPLEXER 14-BIT R REF IN COUNTER LOCK MUTE DETECT CLK 24-BIT 24-BIT DATA FUNCTION DATA REGISTER CHARGE LATCH CP LE PUMP PHASE COMPARATOR V VCO V TUNE C C C N INTEGER REGISTER RF A OUT VCO OUTPUT CORE STAGE 13-BIT B RF B OUT COUNTER LOAD PRESCALER P/P+1 LOAD 5-BIT A COUNTER N = (BP + A) DIVSEL = 1 2 DIVSEL = 2 AGND DGND CPGND Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no re- sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032016 Analog Devices, Inc. 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MULTIPLEXER 04439-001ADF4360-5 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MUXOUT and Lock Detect ...................................................... 10 Applications ....................................................................................... 1 Input Shift Register .................................................................... 10 General Description ......................................................................... 1 VCO ............................................................................................. 10 Functional Block Diagram .............................................................. 1 Output Stage ................................................................................ 11 Revision History ............................................................................... 2 Latch Structure ........................................................................... 12 Specifications ..................................................................................... 3 Power-Up ..................................................................................... 16 Timing Characteristics ..................................................................... 5 Control Latch .............................................................................. 18 Absolute Maximum Ratings ............................................................ 6 N Counter Latch ......................................................................... 19 Transistor Count ........................................................................... 6 R Counter Latch ......................................................................... 19 ESD Caution .................................................................................. 6 Applications Information .............................................................. 20 Pin Configuration and Function Descriptions ............................. 7 Direct Conversion Modulator .................................................. 20 Typical Performance Characteristics ............................................. 8 Fixed Frequency LO ................................................................... 21 Circuit Description ........................................................................... 9 Interfacing ................................................................................... 21 Reference Input Section ............................................................... 9 PCB Design Guidelines for Chip Scale Package........................... 22 Prescaler (P/P + 1) ........................................................................ 9 Output Matching ........................................................................ 22 A and B Counters ......................................................................... 9 Outline Dimensions ....................................................................... 23 R Counter ...................................................................................... 9 Ordering Guide .......................................................................... 23 PFD and Charge Pump ................................................................ 9 REVISION HISTORY 6/2016Rev. B to Rev. C 12/2004Rev. 0 to Rev. A Changed ADF4360 Family to ADF4360-5 and Updated Format .................................................................. Universal ADSP-21xx to ADSP-2181 ........................................... Throughout Changes to Specifications Section ................................................... 3 Updated Outline Dimensions ....................................................... 23 Changes to Timing Characteristics Section ................................... 5 Changes to Ordering Guide .......................................................... 23 Changes to Power-Up Section ...................................................... 16 Added Table 10 ............................................................................... 16 11/2012Rev. A to Rev. B Added Figure 16 ............................................................................. 16 Changes to Table 1 ............................................................................ 4 Changes to Ordering Guide .......................................................... 23 Changes to Table 3 ............................................................................ 6 Updated Outline Dimensions ....................................................... 23 Changes to Figure 3 and Table 4 ..................................................... 7 Changes to Output Matching Section .......................................... 22 11/2003Revision 0: Initial Version Changes to Ordering Guide .......................................................... 23 Rev. C Page 2 of 24