3.3 V/5 VProgrammable PLL Synthesized Clock Generator 50 MHz to 800 MHz NBC12430, NBC12430A www.onsemi.com The NBC12430 and NBC12430A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency MARKING range of 400 MHz to 800 MHz. The VCO frequency is sent to the DIAGRAMS Noutput divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO and output frequency can be programmed 128 using the parallel or serial interfaces to the configuration logic. Output frequency steps of 250 kHz, 500 kHz, 1.0 MHz, 2.0 MHz can be achieved using a 16 MHz crystal, depending on the output dividers NBC12430xG settings. The PLL loop filter is fully integrated and does not require AWLYYWW any external components. PLCC28 FN SUFFIX CASE 776 Features BestinClass Output Jitter Performance, 20 ps PeaktoPeak 50 MHz to 800 MHz Programmable Differential PECL Outputs NBC12 Fully Integrated PhaseLockLoop with Internal Loop Filter 430 Parallel Interface for Programming Counter and Output Dividers AWLYYWWG LQFP32 During Powerup FA SUFFIX Minimal Frequency Overshoot CASE 561AB Serial 3Wire Programming Interface Crystal Oscillator Interface Operating Range: V = 3.135 V to 5.25 V 1 CC CMOS and TTL Compatible Control Inputs NBC12 32 1 430A Pin and Function Compatible with Motorola MC12430 and QFN32 AWLYYWW MPC9230 MN SUFFIX CASE 488AM 0C to 70C Ambient Operating Temperature (NBC12430) 40C to 85C Ambient Operating Temperature (NBC12430A) PbFree Packages are Available x = Blank or A A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. Semiconductor Components Industries, LLC, 2010 1 Publication Order Number: May, 2021 Rev. 14 NBC12430/DNBC12430, NBC12430A +3.3 or 5.0 V 1 1 MHz F PLL V REF CC with 16 MHz Crystal PHASE 16 DETECTOR +3.3 or 5.0 V 3 XTAL SEL VCO 21, 25 2 V CC FREF EXT 24 F N 9BIT M OUT 4 23 2 XTAL1 (1, 2, 4, 8) COUNTER F OUT 400800 MHz 1020MHz OSC 20 5 TEST XTAL2 LATCH LATCH 6 OE 28 S LOAD LATCH 7 P LOAD 01 01 27 S DATA 2BIT SR 3BIT SR 9BIT SR 26 S CLOCK 8 16 17, 18 22, 19 9 2 M 8:0 N 1:0 Figure 1. Block Diagram (PLCC28) Table 1. OUTPUT DIVISION Table 2. XTAL SEL And OE N 1:0 Output Division Input 0 1 0 0 2 XTAL SEL FREF EXT XTAL 0 1 4 OE Outputs Disabled Outputs Enabled 1 0 8 1 1 1 www.onsemi.com 2