Data Sheet ADN4624 5.7 kV RMS/1.5 kV RMS, Quad-Channel LVDS 2.5 Gigabit Isolator FEATURES FUNCTIONAL BLOCK DIAGRAM 5.7 kV rms and 1.5 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS signal levels Quad-channel configuration Any data rate up to 2.5 Gbps switching with low jitter 10 Gbps total bandwidth across four channels 2.15 ns typical propagation delay Typical jitter: 0.82 ps rms random, 40 ps total peak Lower power 1.8 V supplies Figure 1. 8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: 100 kV/s typical GENERAL DESCRIPTION Safety and regulatory approvals (28-lead SOIC W FP package) 1 UL (pending): 5700 V rms for 1 minute per UL 1577 The ADN4624 is a quad-channel, signal isolated, low voltage differential signaling (LVDS) buffer that operates at up to 2.5 Gbps CSA Component Acceptance Notice 5A (pending) with very low jitter. The device integrates Analog Devices, Inc., VDE certificate of conformity (pending) iCoupler technology, enhanced for high speed operation to pro- DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 vide drop-in galvanic isolation of LVDS signal chains. AC coupling V = 849 V (working voltage) IORM PEAK and/or level shifting to the LVDS receivers and from the LVDS Enable or disable refresh (low speed output correctness check) drivers allows isolation of other high speed signals such as current Operating temperature range: 40C to +125C mode logic (CML). 28-lead, wide-body, finer pitch SOIC W FP package with 8.3 The ADN4624 includes a refresh mechanism to monitor the input mm creepage and clearance or 6 mm 6 mm LFCSP package and output states and ensure they remain the same in the absence with 1.27 mm creepage and clearance of data transitions (for example, at power-on). APPLICATIONS For lower power consumption and high speed operation with low jitter, the LVDS and isolator circuits rely on 1.8 V supplies. The Isolated video and imaging data ADN4624 is fully specified over a wide industrial temperature range Analog front-end isolation and is available in a 28-lead, wide-body, finer pitch SOIC W FP Data plane isolation package with 8.3 mm creepage and clearance (for 5.7 kV rms or 8 Isolated high speed clock and data links kV surge and impulse voltages and reinforced insulation at ac PEAK mains voltages) or 6 mm 6 mm LFCSP package with 1.27 mm Multi-gigabit serialization/deserialization (SERDES) creepage and clearance (for basic/functional isolation). Board-to-board optical replacement (for example, short reach fiber) 1 Protected by U.S. Patents 5,952,849 6,873,065 6,903,578 and 7,075,329. Other patents are pending. Rev. A Information furnished by Analog Devices is believed to be accurate and reliableas i. However, no responsibility is assumed by Analog DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and TECHNICAL SUPPORT registered trademarks are the property of their respective owners.Data Sheet ADN4624 TABLE OF CONTENTS Features................................................................ 1 ESD Caution.....................................................10 Applications........................................................... 1 Pin Configurations and Function Descriptions.....11 Functional Block Diagram......................................1 Typical Performance Characteristics...................13 General Description...............................................1 Test Circuits and Switching Characteristics.........17 Specifications........................................................ 3 Theory of Operation.............................................18 Receiver Input Threshold Test Voltages.............4 Isolation and Refresh....................................... 18 Timing Specifications......................................... 4 Truth Table....................................................... 18 Insulation and Safety Related Specifications..... 5 Applications Information...................................... 19 Package Characteristics.....................................6 PCB Layout...................................................... 19 Regulatory Information.......................................6 Application Examples.......................................19 DIN V VDE V 0884-11 (VDE V 0884-11) Magnetic Field Immunity.................................. 20 Insulation Characteristics (Pending).................7 Insulation Lifetime............................................ 21 Recommended Operating Conditions................ 8 Outline Dimensions............................................. 23 Absolute Maximum Ratings...................................9 Ordering Guide.................................................23 Thermal Resistance........................................... 9 Evaluation Boards............................................ 23 Electrostatic Discharge (ESD) Ratings.............10 REVISION HISTORY 10/2021Rev. 0 to Rev. A Added 32-Lead LFCSP....................................................................................................................................1 Changes to Features Section.......................................................................................................................... 1 Changes to General Description Section.........................................................................................................1 Changes to Channel to Channel Parameter and Additive Phase Jitter Parameter, Table 3............................4 Added Table 5 Renumbered Sequentially.......................................................................................................5 Changes to Table 6..........................................................................................................................................6 Added Table 8..................................................................................................................................................6 Change to Figure 2 Caption.............................................................................................................................7 Added Table 10 and Figure 3 Renumbered Sequentially............................................................................... 8 Added Table 14................................................................................................................................................9 Changes to Table 15........................................................................................................................................9 Added Table 17..............................................................................................................................................10 Added Figure 5 and Table 19.........................................................................................................................12 Updated Outline Dimensions......................................................................................................................... 23 Changes to Ordering Guide...........................................................................................................................23 4/2021Revision 0: Initial Version analog.com Rev. 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