SHARC Digital Signal Processor ADSP-21160M/ADSP-21160N SUMMARY FEATURES High performance 32-bit DSPapplications in audio, medi- 100 MHz (10 ns) core instruction rate (ADSP-21160N) cal, military, graphics, imaging, and communication Single-cycle instruction execution, including SIMD opera- Super Harvard architecture4 independent buses for dual tions in both computational units data fetch, instruction fetch, and nonintrusive, zero-over- Dual data address generators (DAGs) with modulo and bit- head I/O reverse addressing Backward compatibleassembly source level compatible Zero-overhead looping and single-cycle loop setup, provid- with code for ADSP-2106x DSPs ing efficient program sequencing Single-instruction, multiple-data (SIMD) computational IEEE 1149.1 JTAG standard Test Access Port and on-chip architecturetwo 32-bit IEEE floating-point computation emulation units, each with a multiplier, ALU, shifter, and register file 400-ball 27 mm 27 mm PBGA package Integrated peripheralsintegrated I/O processor, 4M bits Available in lead-free (RoHS compliant) package on-chip dual-ported SRAM, glueless multiprocessing fea- 200 million fixed-point MACs sustained performance tures, and ports (serial, link, external bus, and JTAG) (ADSP-21160N) CORE PROCESSOR DUAL-PORTED SRAM JTAG INSTRUCTION TIMER TWO INDEPENDENT 6 CACHE DUAL-PORTED BLOCKS TEST AND 32x48-BIT PROCESSOR PORT I/O PORT EMULATION ADDR DATA DATA ADDR DATA ADDR ADDR DATA DAG1 DAG2 PROGRAM 8x4x32 8x 4x 32 SEQUENCER EXTERNAL PORT IOD IOA PM ADDRESS BUS 32 64 18 32 ADDR BUS DM ADDRESS BUS 32 MUX MULTIPROCESSOR INTERFACE PM DATA BUS 16/32/40/48/64 64 BUS DATA BUS CONNECT DM DATA BUS 32/40/64 MUX (PX) HOST PORT DATA DATA REGISTER REGISTER FILE FILE 4 (PEX) (PEY) DMA IOP BARREL BARREL 16x40-BIT 16 x 40-BIT CONTROLLER MULT MULT REGISTERS SHIFTER SHIFTER 6 (MEMORY SERIAL PORTS MAPPED) 6 (2) CONTROL, 60 STATUS AND LINK PORTS ALU ALU DATA BUFFERS (6) I/O PROCESSOR Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2015 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com BLOCK 0 BLOCK 1ADSP-21160M/ADSP-21160N Single-instruction, multiple-data (SIMD) architecture provides Two computational processing elements Concurrent executioneach processing element executes the same instruction, but operates on different data Code compatibilityat assembly level, uses the same instruction set as the ADSP-2106x SHARC DSPs Parallelism in buses and computational units allows Single-cycle execution (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle Accelerated FFT butterfly computation through a multiply with add and subtract Memory attributes 4M bits on-chip dual-ported SRAM for independent access by core processor, host, and DMA 4G word address range for off-chip memory Memory interface supports programmable wait state gen- eration and page-mode for off-chip memory DMA controller supports 14 zero-overhead DMA channels for transfers between ADSP-21160x internal memory and external memory, external peripherals, host processor, serial ports, or link ports 64-bit background DMA transfers at core clock speed, in parallel with full-speed processor execution Host processor interface to 16- and 32-bit microprocessors Multiprocessing support provides Glueless connection for scalable DSP multiprocessing architecture Distributed on-chip bus arbitration for parallel bus con- nect of up to 6 ADSP-21160x processors plus host 6 link ports for point-to-point connectivity and array multiprocessing Serial ports provide Two synchronous serial ports with companding hardware Independent transmit and receive functions TDM support for T1 and E1 interfaces 64-bit-wide synchronous external port provides Glueless connection to asynchronous and SBSRAM exter- nal memories Rev. D Page 2 of 58 September 2015