Blackfin Embedded Processor with Codec ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C PROCESSOR FEATURES EMBEDDED CODEC FEATURES Up to 600 MHz high performance Blackfin processor Stereo, 24-bit ADCs and DACs RISC-like register and instruction model for ease of DAC SNR: 100 dB (A-weighted), THD: 80 dB at 48 kHz, 3.3 V programming and compiler-friendly support ADC SNR: 90 dB (A-weighted), THD: 80 dB at 48 kHz, 3.3 V Advanced debug, trace, and performance monitoring Highly efficient headphone amplifier Accepts a wide range of supply voltages for internal and I/O Stereo line input and monaural microphone input operations. See operating conditions in the published Low power ADSP-BF52x processor data sheet. 7 mW stereo playback (1.8 V supply) Programmable on-chip voltage regulator (ADSP-BF523/ 14 mW record and playback (1.8 V supply) ADSP-BF525/ADSP-BF527processors only) Low supply voltages Embedded low power audio codec Analog: 1.8 V to 3.6 V 289-ball (12 mm x 12 mm) CSP BGA package Digital core: 1.8 V min 132K bytes of on-chip memory Digital I/O: 1.8 V to 3.6 V External memory controller with glueless support for SDRAM 256 f /384 f oversampling rate in normal mode S S and asynchronous 8-bit and 16-bit memories 250 f /272 f oversampling rate in USB mode S S Flexible booting options from external flash, SPI and TWI Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, memory or from host devices including SPI, TWI, and UART 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, Code security with Lockbox Secure Technology and 96 kHz one-time-programmable (OTP) memory PERIPHERALS Memory management unit providing memory protection See the published ADSP-BF52x processor data sheet for 2 dual-channel memory DMA controllers additional peripherals WATCHDOG TIMER OTP MEMORY RTC VOLTAGE REGULATOR* JTAG TEST AND EMULATION COUNTER PERIPHERAL SPORT0 ACCESS BUS SPORT1 INTERRUPT GPIO UART1 CONTROLLER B PORT F UART0 NFC L1 INSTRUCTION L1 DATA DMA GPIO MEMORY MEMORY CONTROLLER DMA PPI PORT G ACCESS EAB 16 CODEC SPI BUS DCB USB TIMER7-1 GPIO DEB PORT H TIMER0 BOOT EXTERNAL PORT EMAC FLASH, SDRAM CONTROL ROM HOST DMA TWI PORT J *REGULATOR AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS ONLY Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2010 Analog Devices, Inc. All rights reserved.ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C TABLE OF CONTENTS Processor Features ................................................... 1 Specifications ........................................................ 21 Embedded Codec Features ......................................... 1 Operating Conditions ........................................... 21 Peripherals ............................................................. 1 Codec Electrical Characteristics .............................. 21 Table of Contents ..................................................... 2 Absolute Maximum Ratings ................................... 23 Revision History ...................................................... 2 ESD Sensitivity ................................................... 23 General Description ................................................. 3 Package Information ............................................ 23 Codec Description ................................................ 3 Power Consumption ............................................ 24 ADC and DAC ..................................................... 4 Timing Specifications ........................................... 25 ADC High-Pass and DAC De-Emphasis Filters ............ 4 TWI Timing ................................................... 25 Analog Audio Interfaces ......................................... 4 SPI Timing ..................................................... 26 Stereo Line and Monaural Microphone Inputs .......... 4 Digital Audio Interface Slave Mode Timing ............ 27 Bypass and Sidetone Paths to Output ...................... 5 Digital Audio Interface Master Mode Timing .......... 28 Line and Headphone Outputs ............................... 5 System Clock Timing ........................................ 29 Digital Audio Interface ........................................... 6 Digital Filter Characteristics ................................ 30 Recording Mode ................................................ 8 Converter Filter Response ..................................... 30 Playback Mode .................................................. 8 Digital De-Emphasis ............................................ 31 Digital Audio Data Sampling Rate .......................... 8 289-Ball CSP BGA Ball Assignment ........................ 32 Software Control Interface .................................... 11 Outline Dimensions ................................................ 35 Codec Pin Descriptions ........................................... 12 Ordering Guide ..................................................... 36 Register Details ..................................................... 15 Bit Descriptions .................................................. 16 REVISION HISTORY 3/10Rev. 0 to Rev. A Revised the following figures. Recommended Application Circuit Using SPI Control .... 13 Recommended Application Circuit Using TWI Control .. 14 Added Sampling Rate = 48 kHz to all figures in Converter Filter Response ........................................ 30 Revised Ordering Guide .......................................... 36 Rev. A Page 2 of 36 March 2010