DEMO CIRCUIT 1348A LT3587EUD QUICK START GUIDE LT3587EUD High Voltage Monolithic Inverter and Dual Boost DESCRIPTION Demonstration Circuit 1348 is a single chip solu- tion for applications requiring two positive and Design files for this circuit board are available. Call one negative high voltage supplies. The input the LTC factory. may be a USB input or a Li-Ion battery equiva- L, LTC, LTM, LT, Burst Mode, OPTI-LOOP, Over-The-Top and PolyPhase are registered lent power source. trademarks of Linear Technology Corporation. Adaptive Power, C-Load, DirectSense, Easy Drive, FilterCAD, Hot Swap, LinearView, Module, Micropower SwitcherCAD, Multimode Dimming, No Latency , No Latency Delta-Sigma, No R , Operational Filter, PanelProtect, SENSE The LT3587EUD is available in a 20-lead (3mm PowerPath, PowerSOT, SmartStart, SoftSpan, Stage Shedding, SwitcherCAD, ThinSOT, UltraFast and VLDO are trademarks of Linear Technology Corporation. Other product names 3mm) QFN surface mount package with ex- may be trademarks of the companies that manufacture the products. posed ground pad. PERFORMANCE SUMMARY Specifications are at T = 25C A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Bus Input Voltage Range 2.5 6.0 V VOUT1 Output Voltage Range IOUT1 0mA to 50mA 14.25 15.75 V VOUT2 Output Voltage Range IOUT2 0mA to 100mA -7.5 -8.5 V VOUT3 Output Voltage Voltage IOUT3 0mA to ILIM3 23.5 26.0 V ILIM VOUT3 Current Limit R equals 8.04k 18 22 mA ILIM OPERATING PRINCIPLES the level at the negative input of A3, the SR latch X1 is reset, turning off the power switch Q1. The level at the negative input of A3 is set by the error All three channels of the LT3587 use a constant amplifier A1, which is simply an amplified version frequency, current mode control scheme to provide of the difference between the reference of 1.24V voltage and/or current regulation at the output. and the feedback voltage. In this manner, the error Operation can be best understood by referring to amplifier sets the correct peak current level to the Block Diagram in Figure 1 of the LT3587 Data keep the output voltage in regulation. If the error Sheet. amplifier output increases, more current is deliv- If EN/SS1 is pulled higher than 200mV, the band- ered to the output: if decreased, less current is de- gap reference, the start-up bias and the oscillator livered. are turned on. At the start of each oscillator cycle, The second channel is an inverting converter. This the SR latch X1 is set, which turns on the power channel is also enabled through the EN/SS1 pin. switch Q1. A voltage proportional to the switch cur- The basic operation of this second channel is the rent is added to a stabilizing ramp and the result- same as the positive channel. The SR latch X2 is ing sum is fed into the positive terminal of the also set at the start of each oscillator cycle. The PWM comparator A3. When this voltage exceeds power switch Q2 is turned on at the same time as 1 LT3587EUD Q1. Q2 turns off based on its own feedback loop, which consists of error amplifier A2 and PWM VOUT1 Output Ripple and Vsw1 Node comparator A4. The reference voltage of this nega- tive channel is ground. Similar to the first channel, the third channel is also a positive boost regulator. If EN/SS3 is pulled higher than 300mV, the bandgap reference, the start-up bias and the oscillators are also turned on. The SR latch X3 is set at the start of each oscilla- tor cycle which turns on the power switch Q3. Q3 turns off based on its own feedback loop, which consists of error amplifier A5 and PWM compara- tor A6. The level at the negative input of A6 is set by the error ampliFer A5, and is an amplified ver- sion of the difference between the reference volt- age of 0.8V and the maximum of the two feedback voltages at VFB3 and IFB3. A separate comparator (not shown) sets the maximum current limit on Q3. The IFB3 pin is pulled up internally with a current that is (1/200) times the load current out of the VOUT3 pin. Therefore, an external resistor con- nected from this pin to ground generates a feed- back voltage proportional to the VOUT3 output load current at the IFB3 pin. When the voltage at VFB3 is higher than the voltage at IFB3, the third channel regulates to the feedback voltage at VFB3, which in normal applications is a divided down voltage from VOUT3. In this state, the third channel behaves as a boost voltage regulator. On the other hand if the voltage at IFB3 is higher, the third channel regulates to the feedback voltage at IFB3, which therefore regulates the VOUT3 output load current to a particular value. In this state, the third channel behaves as a boost current regulator. PMOS M1 is used as an output disconnect pass transistor for the first channel. M1 disconnects the load (VOUT1) from the input as long as the volt- age between CAP1 and VIN is less than 2.5V (typ) and the voltage between CAP1 and VOUT1 is less than 10V (typ). Similarly, PMOS M3 is used as an output disconnect pass transistor for the third VOUT2 Output Ripple, Vsw2 and channel. M3 disconnects the load (VOUT3) from D6 Anode Nodes the input when the third channel is in shutdown VOUT3 Output Ripple and Vsw3 Node (EN/SS3 voltage is lower than 200mV) and the voltage between CAP3 and VOUT3 is less than 10V (typ). 2