DC1653A

DC1653A Oct. 4, 2010 LTC6803-3 Battery Monitor HARDWARE/SOFTWARE USERS GUIDE DESCRIPTION0B Evaluation circuit DC1653A is a Battery Monitoring 1BLTC6803-3 KEY FEATURES System to demonstrate the functional operation of the Separate Cell 0 ADC input (bottom-cell connection). LTC6803-3 integrated circuit. The design includes the Conversion range down to 300mV per cell. ability to daisy-chain up to 10 devices with built-in Robust daisy chain SPI common-mode immunity. board-to-board ribbon-cable interconnects and selec- Packet Error Checking on command writes. tively apply resistive loading to any cell for purposes of 6X lower standby current than LTC6802. Passive Balancing. Additionally, the board includes Power-down mode for no battery drain. an available DC-DC boost conversion section to power Active pullup on discharge-control outputs (S pins). the IC from an isolated external 5V supply. Extensive diagnostic commands. CELLS CONNECTOR 2BDC1653A DEMO FEATURES Controllable discharging for Passive Balancing. Enhanced protection circuitry for IC and external discharge transistors during hot plugging of cells. Graphical User Interface (GUI) screen for demon- DISCHARGE SWITCHES stration of new features and program code devel- opment. Available 60V boost supply from isolated 5V exter- nal supply. Jumper configuration offers 5V offset LTC6803-3 for V to support negative cell readings. Footprint for LTC6655-3.3 calibration reference. DC-DC BOOST BOTTOM TOP PORT PORT DC1653A GETTING STARTED W3B ITH ONE BOARD CONNECTED 5BSINGLE BOARD CONNECTION TO PC AND GUI Step 1. Set jumpers on DC1653A to the default posi- tions indicated in Table 1. B6TABLE 1. JUMPER FUNCTIONS JUMPER FUNCTION DEFAULT DEFAULT POSITION ALTERNATIVE POSITION POSITION Top of Stack (TOS) Active Indicates that the cells monitored by the Allows data to be passed to and from both the JP6 board are at the top of the battery stack. Data Top and Bottom Ports of the board. is not transferred in or out of the Top Port of this board. JP5 General Purpose I/O Active Output connected to pull-up resistor to Vreg. Forced to a logic low level. (GPIO1) Can be programmed as an input or an output. General Purpose I/O Active Output connected to pull-up resistor to Vreg. Forced to a logic low level. JP4 (GPIO2) Can be programmed as an input or an output. JP3 Voltage Mode Active Bottom SPI port is configured as normal TTL Bottom Port is configured as a current inputs (VMODE) voltage level inputs and outputs. Required and outputs. Required setting for all boards on setting for the board on the bottom of the a cell stack above the bottom board. battery cell stack. A 5K PULL-UP RESISTOR MUST BE CONNECTED FROM THE SDO OUTPUT LINE (CONNECTOR J2, PIN 5) TO THE LOGIC POWER RAIL OF THE CIRCUIT DRIVING THE BOTTOM SPI PORT (SEE TEXT). -POWER Stack Connects V- of the LTC6803 to the Cell 0 Forces V- to be at a potential 5V below Cell 0. JP2 potential of the stack. Only usable if separate external power is ap- plied. Permits all cells to properly measure down to -300mV. JP1 +POWER Stack Connects V+ of the LTC6803 to the Cell 12 Connects V+ to the isolated boost power potential of the stack. supply. Only usable if separate external power is applied. Permits full power-down of the LTC6803 when external power is removed. Step 2. Connect DC590B Quick Eval USB cable to When the DC590B Quick Eval board recognizes the PC/Laptop USB port. Connect ribbon cable from String ID code from the DC1653A board, the pro- DC590B to the Bottom Port of DC1653A (J2). gram will open and present the control screen. Make sure that the driver for DC590B has been This sometimes requires two launches of the GUI downloaded from www.linear.HU comHU and installed on program to properly initialize. the computer. This can be verified by running A DC590B board has the required pull-up resistor Quick Eval and seeing the message that there is a to the SDO line already connected. If a system missing module for this board type. Close the other than DC590 is driving the bottom port Quick Eval program and then launch only the con- (which must be set to Voltage Mode) must have a trol program: 5K pull-up resistor added between the SDO line LTC6803-1-3 GUI Vxx yyyymmdd.exe (J2, PIN 5) and the 3V/5V logic supply rail of the 2