DEMO MANUAL DC1839A LTC3634 15V Dual 3A Monolithic Step-Down Regulator Board for DDR Power DESCRIPTION Demonstration circuit 1839A is a dual output regulator forced continuous mode. In Burst Mode operation, which focused specifically for DDR memory power applications. is the preferred mode of low load current operation, the DC Its built based on the LTC3634, a high voltage dual channel, supply current is typically only 1.3mA (both channels) at controlled on-time monolithic synchronous buck regulator. no load (sleep mode), and less than 15A in shutdown. In The DC1839A has an input voltage range of 3.6V to 15V. The Burst Mode operation or continuous mode operation, the output voltage of the first channel, V , of the DC1839A DC1839A is a very efficient circuit at high load currents: DDQ has three fixed voltage settings 1.5V, 1.8V, and 2.5V, and over 80% for either channel. The LTC3634 is also capable is capable of delivering up to 3A of output current. The of in-phase or 180 out-of-phase operation, and to allow second channel, V , is set to regulate to half the voltage its output to track an external voltage, either coincidentally TT on the VDDQIN pin, which can be either the channel1 or ratiometrically. The LTC3634 comes in a 28-pin QFN or output or an external reference voltage. It can source or leaded package, which each having an exposed pad on sink a maximum of 3A. The LTC3634 also provides a 10mA the bottom side of the IC for better thermal performance. buffered output of half VDDQIN VTTR, which is used to All of these features make the DC1839A an ideal circuit provide the reference voltage needed for DDR applications. for powering DDR memory applications. With the use of a timing resistor, the DC1839A can have its Design files for this circuit board are available at operating frequency programmed from 500kHz to 4MHz, DEMO MANUAL DC1839A QUICK START PROCEDURE The DC1839A is easy to set up to evaluate the performance resistor from V to V , along with an ampmeter. The IN OUT of the LTC3634. For a proper measurement equipment current will be V minus V divided by the variable IN OUT configuration, set up the circuit according to the diagram resistor value). V output voltage tolerance should DDQ in Figure 1. be within 2%, whereas the output voltage tolerance of V should be within 3%. TT NOTE: When measuring the input or output voltage ripple, care must be taken to avoid a long ground lead on the 5. Set the load current of both outputs to 3A and the input oscilloscope probe. Measure the input or output voltage voltage to 12V, then measure each output ripple voltage ripple by touching the probe tip directly across the V (refer to Figure 2 for proper measurement technique) IN or V and GND terminals. See the proper scope probe they should each measure less than 20mVAC. Also, OUT technique in Figure 2. observe the voltage waveform at either switch node (pins 16 and 17 for channel 1, and 23 and 24 for chan- Please follow the procedure outlined below for proper nel 2) of each regulator. (Both switch node waveforms operation. should be rectangular in shape and 180out-of-phase 1. Connect the input power supply to the V and GND IN with each other). The switching frequencies should be terminals. Connect the loads between the V and GND OUT between 800kHz and 1.2MHz (T = 1.25s and 0.833s). terminals. Refer to Figure 1 for the proper measurement 6. With the board under proper operation, observe the load equipment setup. regulation, efficiency, in-phase operation (by changing Before proceeding to operation, insert jumper shunts jumper XJP4 to the 90 position), or BurstMode op- XJP1 and XJP2 into the OFF positions of headers JP1 eration (by changing jumper XJP3 to the Burst Mode and JP2, shunt XJP3 into the forced continuous mode position). (FCM) position of MODE header JP3, shunt XJP4 into 7. (Optional) Moving the zero ohm resistor at RV , DDQ the 180 (out-of-phase) position of PHASE header JP4, inserting it into R , and applying a voltage to turret DDQIN shunt XJP5 into the soft-start positions of TRACK/SS V allows channel2 output voltage (VTTR) to be DDQIN header JP5, and shunt XJP6 into the V voltage OUT1 adjusted to any desired voltage (to one-half the voltage options of choice of header JP6: 1.2V, 1.5V, or 1.8V. at VDDQIN). 2. Apply 5V at V . Measure both V s they should read IN OUT When finished, insert shunts XJP1 and XJP2 to the OFF 0V. If desired, one can measure the shutdown supply position(s) and disconnect the power. current at this point. The supply current should be less than 30A in shutdown. Warning: If the power for the demo board is carried in long leads, the input voltage at the part could ring, which 3. Turn on V , V , and V , V , by shifting shunts OUT1 DDQ OUT2 TT could affect the operation of the circuit or even exceed XJP1 and XJP2 from the OFF positions to the ON posi- the maximum voltage rating of the IC. To eliminate the tions. Both output voltages should be within a tolerance ringing, a small Poscap capacitor (for instance, AVX part of 1%. number TPSY226M035R0200) is inserted on the pads 4. Vary the input voltage from 3.6V to 15V, the channel 1 between the input power and return terminals on the bot- load current from 0 to 3A, and the channel 2 load cur- tom of the demo board. The (greater) ESR of the Poscap rent from 0 to 3A (The V channel sinks as well as TT will dampen the (possible) ringing voltage due to the use sources current. An easy way to test this capability is of long input leads. On a normal, typical PCB, with short shown in the test set-up diagram connect a variable traces, this capacitor is not needed. dc1839af 2