Product Information

DC1954A-C

DC1954A-C electronic component of Analog Devices

Datasheet
Clock & Timer Development Tools LTC6954-3 Demo Board Low Phase Noise, Triple Output Clock Distribution Divider/Driver, 1 LVPECL and 2 LVDS/CMOS outputs (Req DC590 or DC2026)

Manufacturer: Analog Devices
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 311.7395 ea
Line Total: USD 311.74

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
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0 - WHS 1


Ships to you between Wed. 22 May to Tue. 28 May

MOQ : 1
Multiples : 1

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DC1954A-C
Analog Devices

1 : USD 322.639

0 - WHS 2


Ships to you between Tue. 28 May to Thu. 30 May

MOQ : 1
Multiples : 1

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DC1954A-C
Analog Devices

1 : USD 194.6398

     
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LTC6954 Low Phase Noise, Triple Output Clock Distribution Divider/Driver FEATURES DESCRIPTION n Low Noise Clock Distribution: Suitable for High The LTC 6954 is a family of very low phase noise clock Speed/High Resolution ADC Clocking distribution parts. Each part has three outputs and each n Additive Jitter < 20fs (12kHz to 20MHz) output has an individually programmable frequency RMS n Additive Jitter < 85fs (10Hz to Nyquist) divider and delay. There are four members of the family, RMS n 1.8GHz Maximum Input Frequency differing in their output logic signal type: (LTC6954-1 When DELAY = 0) LTC6954-1: Three LVPECL outputs n 1.4GHz Maximum Input Frequency LTC6954-2: Two LVPECL and one LVDS/CMOS outputs (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) n LTC6954-3: One LVPECL and two LVDS/CMOS outputs EZSync Clock Synchronization Compatible n Three Independent, Low Noise Outputs LTC6954-4: Three LVDS/CMOS outputs n Four Output Combinations Available Each output is individually programmable to divide the n Three Independent Programmable Dividers Covering input frequency by any integer from 1 to 63, and to delay All Integers from 1 to 63 each output by 0 to 63 input clock cycles. The output duty n Three Independent Programmable Delays Covering cycle is always 50%, regardless of the divide number. All Integers from 0 to 63 The LVDS/CMOS outputs are jumper selectable via the n 40C to 105C Junction Temperature Range OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output. APPLICATIONS The LTC6954 also features Linear Technologys EZSync n Clocking High Speed, High Resolution ADCs, DACs system for perfect clock synchronization and alignment and Data Acquisition Systems every time. n Low Jitter Clock Distribution All device settings are controlled through an SPI-compatible All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 8319551, 8819472. serial port. TYPICAL APPLICATION Additive Phase Noise vs Offset Frequency, 0.1F 3.3V f = 622.08MHz, Mx 5:0 = 4, IN UP TO 1.4GHz f = 155.52MHz OUTx 120 + + 49.9 IN V LTC6954-3 IN + 130 OUT0 49.9 LVPECL OUTPUT 49.9 DELAY DIVIDE FREQUENCY SYNC OUT0 SYNC 0 TO 63 1 TO 63 UP TO 1.8GHz 140 CONTROL + OUT1 OUT0SEL LVDS OUTPUT DELAY DIVIDE 150 FREQUENCY OUT1 0 TO 63 1 TO 63 OUT1SEL UP TO 1.4GHz 3.3V + OUT2SEL SERIAL OUT2 160 CMOS OUTPUT PORT DELAY DIVIDE SDO FREQUENCY OUT2 AND 0 TO 63 1 TO 63 UP TO 250MHz 170 DIGITAL SDI SPI SERIAL SCLK 180 PORT 10 100 1k 10k 100k 1M 10M CS GND OFFSET FREQUENCY (Hz) 6954 TA01a 6954 TA01b Rev. A 1 Document Feedback For more information www.analog.com ADDITIVE PHASE NOISE (dBc/Hz)LTC6954 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW Supply Voltages + + + + + (V , V , V , V , V and A D IN OUT0 OUT1 + V to GND) ........................................................3.6V OUT2 36 35 34 33 32 31 LTC6954-1, -2, -3 LVPECL Outputs + + V 1 30 V OUT2 IN + OUTx Output Voltage High ......................V + 0.3V OUT OUT2 2 29 GND OUTx Output Voltage Low ..................... Source 25mA + OUT2 3 28 IN LTC6954-2, -3, -4 LVDS/CMOS Outputs + + V 4 27 IN OUT2 + + OUTx ..........................................0.3V to (V +0.3V) V 5 26 GND A OUT1 + OUT1 6 25 V TEMP Input Current ...............................................10mA 37 IN + GND + OUT1 7 24 V A TEMP Low Voltage ................................................0.3V + + + V 8 23 V OUT1 A Voltage on All Other Pins ..............0.3V to (V + 0.3V) A + V 9 22 SYNC OUT0 Operating Junction Temperature Range, T (Note 2) J + OUT0 V 10 21 D LTC6954I ............................................... 40C to 105C + OUT0 11 20 SDI Junction Temperature, T ................................ 150C JMAX + V SCLK 12 19 OUT0 Storage Temperature Range .................. 65C to 150C 13 14 15 16 17 18 UFF PACKAGE 36-LEAD (4mm 7mm) PLASTIC QFN 0.5mm LEAD PITCH T = 150C, = 2C/W, = 18C/W JMAX JCbottom JCtop EXPOSED PAD (PIN 37) IS GND, MUST BE SOLDERED TO PCB GND ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION JUNCTION TEMPERATURE RANGE LTC6954IUFF-1 PBF LTC6954IUFF-1 TRPBF 69541 36-Lead (4mm 7mm) Plastic QFN 40C to 105C LTC6954IUFF-2 PBF LTC6954IUFF-2 TRPBF 69542 36-Lead (4mm 7mm) Plastic QFN 40C to 105C LTC6954IUFF-3 PBF LTC6954IUFF-3 TRPBF 69543 36-Lead (4mm 7mm) Plastic QFN 40C to 105C LTC6954IUFF-4 PBF LTC6954IUFF-4 TRPBF 69544 36-Lead (4mm 7mm) Plastic QFN 40C to 105C Contact the factory for parts specified with wider operating temperature ranges. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with TRMPBF suffix. Rev. A 2 For more information www.analog.com OUT0SEL OUT2SEL GND GND + + V V A A CS OUT1SEL SDO GND + V TEMP D

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