DEMO MANUAL DC2290A LTC2387/LTC2386/LTC2385 18-/16-Bit, 15Msps/10Msps/5Msps, High Speed SAR ADCs Description Demonstration circuit 2290A features the LTC 2387 family. board. Differential amplifier demo boards are available With up to 15Msps, these differential input, single channel, separately that provide amplification of low level differ- 18-/16-Bit, serial, high speed successive approximation ential signals if required (see Table 2). Alternatively, by register (SAR) ADCs are available in a 32-Pin QFN package. connecting the DC2290A into a customer application the The LTC2387 family has an internal 20ppm/C reference performance of the LTC2387 can be evaluated directly in and a serial LVDS interface. The following text refers to that circuit. the LTC2387 but applies to all members of the family, the Design files for this circuit board are available at only difference being the sample rate and the number of DEMO MANUAL DC2290A Dc 718 Quick s p D Connect the DC2290A to a DC718 USB High Speed Data cies. Note that J4 has a 50 termination resistor to ground. Collection Board using edge connector J1. Connect the Run the PScope software (Pscope.exe version K73 or DC718 to a host PC with a standard USB A/B cable. Apply later) supplied with DC718 or download it from www. + a low noise differential signal to J6 (A ) and J5 (A ). linear.com/software. Complete software documentation is IN IN Note that the DC2290A requires a differential input signal available from the Help menu. Updates can be downloaded of approximately 8.192V peak-to-peak to reach 0dBFS. If a from the Tools menu. Check for updates periodically as differential signal source of this amplitude is not available new features may be added. The PScope software should use one of the recommended differential amplifier demo recognize the DC2290A and configure itself automatically. boards available to increase the signal level. For a clock Click the Collect button (Figure 2) to begin acquiring data. source, apply a low jitter 10dBm sine wave or square wave The Collect button then changes to Pause, which can be to connector J4. See Table 1 for maximum clock frequen- used to stop data acquisition. Table 1. DC2290A Assembly Options VERSION U1 PART NUMBER MAX CONVERSION RATE OF BITS MAX CLOCK FREQUENCY DC2290A-A LTC2387CUH-18 PBF 15Msps 18 15MHz DC2290A-B LTC2387CUH-16 PBF 15Msps 16 15MHz DC2290A-C LTC2386CUH-18 PBF 10Msps 18 10MHz DC2290A-D LTC2386CUH-16 PBF 10Msps 16 10MHz DC2290A-E LTC2385CUH-18 PBF 5Msps 18 5MHz DC2290A-F LTC2385CUH-16 PBF 5Msps 16 5MHz h D s SIGNAL CONNECTIONS JUMPERS J2: JTAG. Factory use only. JP1: EEPROM. Factory use only. J3: FPGA Program. Factory use only. JP2: Lanes. Use this jumper to select either single lane or two lane data output mode from the LTC2387. The default J4: CLK IN. This input has a 50 termination resistor, setting is 1. The 1 setting clocks out all data on pin DA of and is intended to be driven by a low jitter, 10dBm sine the LTC2387. The 2 setting clocks out data alternately on or square wave. To achieve full AC performance of this pins DA and DB of the LTC2387. part, the clock jitter should be kept under 2ps . This RMS input is capacitively coupled so that the input clock can JP3: Test Pattern. Use this jumper to deliver a fixed repeat- be either 0V to 3.3V or 1.65V. This eliminates the need ing test pattern from the LTC2387. The default setting is for level shifting. To run at the maximum conversion rate, OFF. The output data will be 97796 if the jumper is in apply the frequency specified in Table 1. the ON position in 1 lane mode, and will be 52996 in 2 lane mode. J5: A Input. This is the negative signal input. IN JP4: ADC ON. Use this jumper to enable or disable the + J6: A Input. This is the positive signal input. IN ADC. The default setting is ON. dc2290afb 2 etup ware ar ure roce tart