Click here to ask about the production status of specific part numbers. Evaluates: MAX13035E MAX13035E Evaluation Kit General Description Features The MAX13035E evaluation kit (EV kit) demonstrates Supply Voltage Ranges the MAX13035E 6-channel, bidirectional logic-level V : 1.62V to 3.2V L translator used for interfacing with secure digital (SD) V : 2.2V to 3.6V CC memory cards. The EV kit features SD memory card 15kV ESD Protection on I/O V Lines CC interface and general-purpose interface connections. The SD Memory Card and General-Purpose Interface MAX13035E IC guarantees data rates up to 100Mbps. Connections The MAX13035E translates between V and V logic L CC levels. The V range is 1.62V to 3.2V and the 15kV 100Mbps Guaranteed Data Rates L ESD-protected V range is 2.2V to 3.6V. CC Fully Assembled and Tested The EV kit also includes the MAX3202E, a dual-channel ESD protection array for complete line protection. Component List Ordering Information PART TEMP RANGE IC PACKAGE DESIGNATION QTY DESCRIPTION MAX13035EEVKIT 0C to +70C* 16 UCSP 4.7F 10%, 6.3V X5R ceramic C1, C2 2 capacitors (0603) Denotes RoHS compliant EV kit. Murata GRM188R60J475K *This limited temperature range applies to the EV kit PCB only. The MAX13035E IC temperature range is -40C to +85C. 1F 10%, 10V X5R ceramic C3, C5, C8 3 capacitors (0603) Component Supplier Murata GRM188R61A105K 0.1F 10%, 10V X5R ceramic SUPPLIER WEBSITE WEBSITE C4, C6, C7 3 capacitors (0402) Murata Mfg. Co., Ltd. 770-436-1300 www.murata.com Murata GRM155R61A104K Note: Indicate that you are using the MAX13035E when J1 1 2 x 11-pin header contacting this component supplier. J2 1 SD/MMC 9-pin connector JU1, JU2 2 2-pin headers R1R9 9 0 5% resistors (0402) R10, R11 2 100k 5% resistors (0603) TP1TP6 0 Not installed, test points TP7, TP8 2 Black PCB test points U1 1 MAX13035EETE+ (16-pin TQFN) 15kV ESD-protection array IC (6-pin TQFN-EP-6) U2 1 Maxim MAX3202EETT+ (Top Mark: ADQ) 2 Shunts (JU1, JU2) 1 PCB: MAX13035E Evaluation Kit 19-0801 Rev 2 12/20Evaluates: MAX13035E MAX13035E Evaluation Kit Table 1. I/O Interface Header J1 Pinout Quick Start Recommended Equipment J1 PIN* EV KIT SIGNAL 2VDC power supply 2 I/O V 3 L 3VDC power supply 4 I/O V 2 L Logic function generator 6 V L Oscilloscope 8 I/O V 1 L Procedure 10 V CC The MAX13035E EV kit is fully assembled and tested. 12 CLK V L Follow the steps below to verify board operation. Caution: 14 CLK RET Do not turn on the power supply until all connections are completed. 16 I/O V 5 L 1) Verify that shunts are not installed on jumpers JU1 18 I/O V 4 L (card detect pulled high) and JU2 (write protect 20 CD pulled high). 22 WP 2) Set the logic function generator to produce a 1MHz, 2V , 1V offset square wave. Disable the logic P-P *All odd pins are connected to ground (GND). function generator output. Terminate the function generator as necessary. Detailed Description 3) Connect the positive terminal of the 2V supply to the The MAX13035E EV kit circuit demonstrates the VL PCB pad, and the ground terminal to the GND MAX13035E 6-channel, bidirectional logic-level transla- PCB pad. tor. The EV kit features an SD memory card interface, 4) Connect the positive terminal of the 3V supply to the input/output (I/O) test points (TP1TP6), GND test points (TP7, TP8), and header J1 for general-purpose VCC PCB pad, and the ground terminal to the GND PCB pad. interfacing. The MAX13035E guarantees data rates up to 100Mbps and demonstrates the MAX13035E 15kV 5) Connect the logic function generator to pin 8 of ESD protection. The MAX13035E translates between V L header J1 and the ground lead to pin 7 of header J1. and V logic levels. The V supply input range is 1.62V CC L 6) Connect the oscilloscope to test point TP1. Use test to 3.2V, while the V supply input range is 2.2V to 3.6V. CC point TP8 as a ground reference for the oscilloscope. V must be set higher than V . CC L 7) Enable the power supplies and the logic function The MAX13035E EV kit circuit features I/O traces of generator output. matched length (within 30 mils) to maintain propagation- 8) Using the oscilloscope, verify that TP1 shows a 1MHz, time uniformity. Jumpers JU1 and JU2 set the status 3V square wave. signals for card detect (CD) and write protect (WP), P-P respectively. CD and WP are ESD-protected to 15kV by Note: All odd-number pins of header J1 are connected to a MAX3202E IC (U2). GND. See Table 1 for even-number pins signals. I/O Interface Header J1 Header J1 provides access to the circuits V logic- L level I/O signals, power input lines, and status signals (CD and WP). Use either the PCB pads for VCC and VL, or the corresponding pins on J1 (pins 10 and 6, respec- tively) to power the kit. Use the CD and WP pins on J1 to monitor the card-detect and write-protect status signals. I/O V 1I/O V 5 and CLK V are the EV kits V L L L L referenced logic signals. CLK RET is the returned signal at a clock applied to CLK V . CLK RET is referenced to V . L L Maxim Integrated 2 www.maximintegrated.com